[XL] Change in coreboot[main]: mb/lenovo: Add ThinkCentre M920q (Cannon Lake)

[Angel Pons (Code Review)]

Attention is currently required from: Alexander Couzens, Maciej Pijanowski, Paul Menzel.

Angel Pons has posted comments on this change by Maciej Pijanowski. ( https://review.coreboot.org/c/coreboot/+/80609?usp=email )

Change subject: mb/lenovo: Add ThinkCentre M920q (Cannon Lake)
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Patch Set 7:

(1 comment)

File src/mainboard/lenovo/m920q/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/80609/comment/9b0247b6_6d502631?usp... :
PS7, Line 57: 
            : 		# not populated on M920q. Appears to be populated on M920x
            : 		# variant but it was not tested in any way so far.
            : 
            : 		device ref pcie_rp21 on # M.2 SSD #1
            : 			register "PcieRpSlotImplemented[20]"	= "1"
            : 			register "PcieRpEnable[20]"		= "1"
            : 			register "PcieClkSrcUsage[4]"		= "20"
            : 			register "PcieClkSrcClkReq[4]"		= "4"
            : 		end
            : 
            : 		device ref pcie_rp9	on # WLAN
            : 			register "PcieRpSlotImplemented[8]"	= "1"
            : 			register "PcieRpEnable[5]"		= "1"
            : 			register "PcieClkSrcUsage[3]"		= "5"
            : 			register "PcieClkSrcClkReq[3]"		= "3"
            : 		end
I'm not sure where this info comes from, but it doesn't match the schematics I have. Also, WLAN (`device ref pcie_rp9`) is enabling PCIe RP #6, which is wrong...

```suggestion
    	device ref pcie_rp6	on # WLAN
    		register "PcieRpEnable[5]"		= "1"
    		register "PcieRpSlotImplemented[5]"	= "1"
    		register "PcieClkSrcUsage[3]"		= "5"
    		register "PcieClkSrcClkReq[3]"		= "3"
    	end

device ref pcie_rp9	on # PCIe x4
    		register "PcieRpEnable[8]"		= "1"
    		register "PcieRpSlotImplemented[8]"	= "1"
    		register "PcieClkSrcUsage[2]"		= "8"
    		register "PcieClkSrcClkReq[2]"		= "2"
    	end

device ref pcie_rp17 on # M.2 SSD #2
    		register "PcieRpEnable[16]"		= "1"
    		register "PcieRpSlotImplemented[16]"	= "1"
    		register "PcieClkSrcUsage[10]"		= "16"
    		register "PcieClkSrcClkReq[10]"		= "10"
    	end

device ref pcie_rp21 on # M.2 SSD #1
    		register "PcieRpEnable[20]"		= "1"
    		register "PcieRpSlotImplemented[20]"	= "1"
    		register "PcieClkSrcUsage[4]"		= "20"
    		register "PcieClkSrcClkReq[4]"		= "4"
    	end
```