Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43485 )
Change subject: soc/amd/stoneyridge: Remove unused SPI #defines ......................................................................
soc/amd/stoneyridge: Remove unused SPI #defines
These #defines are not used, and conflict with #defines in amdblocks/spi.h
BUG=None TEST=Build stoney platforms
Signed-off-by: Martin Roth martin@coreboot.org Change-Id: I29b77a6b21a4deda6f28f5b057988cf3921540e2 --- M src/soc/amd/stoneyridge/include/soc/southbridge.h 1 file changed, 0 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/43485/1
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 601cead..80c258f 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -255,8 +255,6 @@ #define SPI_FIFO_PTR_CLR BIT(20) #define SPI_ARB_ENABLE BIT(19) #define EXEC_OPCODE BIT(16) -#define SPI_FIFO 0x80 -#define SPI_FIFO_DEPTH (0xc7 - SPI_FIFO)
#define SPI100_ENABLE 0x20 #define SPI_USE_SPI100 BIT(0)
Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43485 )
Change subject: soc/amd/stoneyridge: Remove unused SPI #defines ......................................................................
Patch Set 1: Code-Review+1
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43485 )
Change subject: soc/amd/stoneyridge: Remove unused SPI #defines ......................................................................
Patch Set 1: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43485 )
Change subject: soc/amd/stoneyridge: Remove unused SPI #defines ......................................................................
Patch Set 1: Code-Review+2
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43485 )
Change subject: soc/amd/stoneyridge: Remove unused SPI #defines ......................................................................
Patch Set 1: Code-Review+2
Aaron Durbin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43485 )
Change subject: soc/amd/stoneyridge: Remove unused SPI #defines ......................................................................
soc/amd/stoneyridge: Remove unused SPI #defines
These #defines are not used, and conflict with #defines in amdblocks/spi.h
BUG=None TEST=Build stoney platforms
Signed-off-by: Martin Roth martin@coreboot.org Change-Id: I29b77a6b21a4deda6f28f5b057988cf3921540e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43485 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Rob Barnes robbarnes@google.com Reviewed-by: Aaron Durbin adurbin@chromium.org Reviewed-by: Furquan Shaikh furquan@google.com Reviewed-by: Raul Rangel rrangel@chromium.org --- M src/soc/amd/stoneyridge/include/soc/southbridge.h 1 file changed, 0 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Furquan Shaikh: Looks good to me, approved Raul Rangel: Looks good to me, approved Rob Barnes: Looks good to me, but someone else must approve
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 601cead..80c258f 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -255,8 +255,6 @@ #define SPI_FIFO_PTR_CLR BIT(20) #define SPI_ARB_ENABLE BIT(19) #define EXEC_OPCODE BIT(16) -#define SPI_FIFO 0x80 -#define SPI_FIFO_DEPTH (0xc7 - SPI_FIFO)
#define SPI100_ENABLE 0x20 #define SPI_USE_SPI100 BIT(0)
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Aaron Durbin (Code Review) -
Furquan Shaikh (Code Review)
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Martin Roth (Code Review)
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Raul Rangel (Code Review)
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Rob Barnes (Code Review)