Change in coreboot[master]: soc/rockchip/rk3399/sdram: Introduce pctl_start

[Moritz Fischer (Code Review)]

Attention is currently required from: Julius Werner.
Moritz Fischer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51129 )

Change subject: soc/rockchip/rk3399/sdram: Introduce pctl_start
......................................................................

soc/rockchip/rk3399/sdram: Introduce pctl_start

Adapted from u-boot commit a0aebe8398 ("ram: rk3399: Add pctl start
support")

Contains fix from u-boot commit 410d7863bc ("ram: rk3399: fix error
about get_ddrc0_con reg addr")

Change-Id: Idcea403218ba96ec48c889709b73df4e8882d825
Signed-off-by: Moritz Fischer 
---
M src/soc/rockchip/rk3399/sdram.c
1 file changed, 49 insertions(+), 13 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/51129/1

diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c
index 718cc02..c7982f9 100644
--- a/src/soc/rockchip/rk3399/sdram.c
+++ b/src/soc/rockchip/rk3399/sdram.c
@@ -94,6 +94,11 @@

u32 pwrup_srefresh_exit[MAX_DRAM_CHANNELS];

+static void *get_ddrc0_con(u32 channel)
+{
+	return channel ? &rk3399_grf->ddrc1_con0 : &rk3399_grf->ddrc0_con0;
+}
+
 static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
 {
    int i;
@@ -331,6 +336,44 @@
    clrsetbits32(&denali_phy[930], 0x1 << 17, reg_value);
 }

+static int pctl_start(u32 channel)
+{
+	u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy;
+	u32 *denali_ctl = rk3399_ddr_pctl[channel]->denali_ctl;
+	u32 *ddrc0_con = get_ddrc0_con(channel);
+	struct stopwatch sw;
+	u32 byte, tmp;
+
+	write32(&ddrc0_con, 0x01000000);
+
+	clrsetbits32(&denali_phy[957], 0x3 << 24, 0x2 << 24);
+
+	stopwatch_init_msecs_expire(&sw, 100);
+	while (!(read32(&denali_ctl[203]) & (1 << 3))) {
+		if (stopwatch_expired(&sw)) {
+			printk(BIOS_ERR, "Failed to init pctl for channel %d\n",
+			       channel);
+			return -1;
+		}
+	}
+
+	write32(&ddrc0_con, 0x01000100);
+
+	for (byte = 0; byte < 4; byte++) {
+		tmp = 0x820;
+		write32(&denali_phy[53 + (128 * byte)], (tmp << 16) | tmp);
+		write32(&denali_phy[54 + (128 * byte)], (tmp << 16) | tmp);
+		write32(&denali_phy[55 + (128 * byte)], (tmp << 16) | tmp);
+		write32(&denali_phy[56 + (128 * byte)], (tmp << 16) | tmp);
+		write32(&denali_phy[57 + (128 * byte)], (tmp << 16) | tmp);
+
+		clrsetbits32(&denali_phy[58 + (128 * byte)], 0xffff, tmp);
+	}
+
+	clrsetbits32(&denali_ctl[68], PWRUP_SREFRESH_EXIT, pwrup_srefresh_exit[channel]);
+	return 0;
+}
+
 static void phy_io_config(u32 channel, const struct rk3399_sdram_params *params)
 {
    u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy;
@@ -489,7 +532,6 @@
    const u32 *params_ctl = params->pctl_regs.denali_ctl;
    const u32 *params_phy = params->phy_regs.denali_phy;
    u32 tmp, tmp1, tmp2;
-	struct stopwatch sw;

/*
     * work around controller bug:
@@ -565,18 +607,6 @@

phy_io_config(channel, params);

-	/* PHY_DLL_RST_EN */
-	clrsetbits32(&denali_phy[957], 0x3 << 24, 0x2 << 24);
-
-	/* FIXME: need to care ERROR bit */
-	stopwatch_init_msecs_expire(&sw, 100);
-	while (!(read32(&denali_ctl[203]) & (1 << 3))) {
-		if (stopwatch_expired(&sw))
-			return -1;
-	}
-
-	clrsetbits32(&denali_ctl[68], PWRUP_SREFRESH_EXIT,
-		     pwrup_srefresh_exit[channel]);
    return 0;
 }

@@ -1140,6 +1170,12 @@
    		board_reset();
    	}

+		/* start to trigger initialization */
+		if (pctl_start(channel)) {
+			printk(BIOS_ERR, "Channel %d pctl_start fail\n", channel);
+			board_reset();
+		}
+
    	/* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
    	if (dramtype == LPDDR3)
    		udelay(10);