Change in coreboot[master]: [WIP] ChromeOS: Refactor SMBIOS type0 bios_version()

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49281 )

Change subject: [WIP] ChromeOS: Refactor SMBIOS type0 bios_version()
......................................................................

[WIP] ChromeOS: Refactor SMBIOS type0 bios_version()

Pointer to an empty string (filled with spaces) is
stored inside GNVS and depthcharge fills it in?

Change-Id: I9405afbea29b896488b4cdd6dd32c4db686fe48c
Signed-off-by: Kyösti Mälkki 
---
M src/acpi/chromeos-gnvs.c
M src/arch/x86/smbios.c
M src/include/acpi/acpi_gnvs.h
3 files changed, 23 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/49281/1

diff --git a/src/acpi/chromeos-gnvs.c b/src/acpi/chromeos-gnvs.c
index 8d96769..ff073f3 100644
--- a/src/acpi/chromeos-gnvs.c
+++ b/src/acpi/chromeos-gnvs.c
@@ -27,3 +27,13 @@

gnvs_chromeos->vbt2 = ACTIVE_ECFW_RW;
 }
+
+void gnvs_set_vbt10(void)
+{
+	chromeos_acpi_t *gnvs_chromeos = gnvs_chromeos_ptr(acpi_get_gnvs());
+	if (!gnvs_chromeos)
+		return;
+
+	/* Location of smbios_type0.bios_version() string filled with spaces. */
+	gnvs_chromeos->vbt10 = smbios_type0_bios_version_address();
+}
diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c
index aaf989d..8ab7c05 100644
--- a/src/arch/x86/smbios.c
+++ b/src/arch/x86/smbios.c
@@ -16,9 +16,6 @@
 #include <device/pci_ids.h>
 #include <device/pci_def.h>
 #include <device/pci.h>
-#if CONFIG(CHROMEOS)
-#include <vendorcode/google/chromeos/gnvs.h>
-#endif
 #include <drivers/vpd/vpd.h>
 #include <stdlib.h>

@@ -398,6 +395,13 @@
    return coreboot_version;
 }

+static uintptr_t bios_version_address;
+
+uintptr_t smbios_type0_bios_version_address(void)
+{
+	return bios_version_address;
+}
+
 static int smbios_write_type0(unsigned long *current, int handle)
 {
    struct smbios_type0 *t = (struct smbios_type0 *)*current;
@@ -411,11 +415,11 @@
    t->vendor = smbios_add_string(t->eos, "coreboot");
    t->bios_release_date = smbios_add_string(t->eos, coreboot_dmi_date);

-#if CONFIG(CHROMEOS) && CONFIG(HAVE_ACPI_TABLES)
-	u32 version_offset = (u32)smbios_string_table_len(t->eos);
-	/* SMBIOS offsets start at 1 rather than 0 */
-	chromeos_get_chromeos_acpi()->vbt10 = (uintptr_t)t->eos + (version_offset - 1);
-#endif
+	if (CONFIG(CHROMEOS)) {
+		/* SMBIOS offsets start at 1 rather than 0 */
+		bios_version_address = (uintptr_t)t->eos;
+		bios_version_address += (u32)smbios_string_table_len(t->eos) - 1;
+	}
    t->bios_version = smbios_add_string(t->eos, get_bios_version());
    uint32_t rom_size = CONFIG_ROM_SIZE;
    rom_size = MIN(CONFIG_ROM_SIZE, 16 * MiB);
diff --git a/src/include/acpi/acpi_gnvs.h b/src/include/acpi/acpi_gnvs.h
index b5f65ca..32aaf28 100644
--- a/src/include/acpi/acpi_gnvs.h
+++ b/src/include/acpi/acpi_gnvs.h
@@ -11,6 +11,7 @@

void gnvs_assign_chromeos(void);
 void gnvs_set_ecfw_rw(void);
+void gnvs_set_vbt10(uintptr_t bios_version);

/* Platform code must implement these. */
 struct global_nvs;