Change in coreboot[master]: soc/intel/common/cse: Perform cse_fw_sync on BS_PRE_DEVICE entry
Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48130 )
Change subject: soc/intel/common/cse: Perform cse_fw_sync on BS_PRE_DEVICE entry ......................................................................
soc/intel/common/cse: Perform cse_fw_sync on BS_PRE_DEVICE entry
This change drops the special check added for TGL/JSL platforms and performs cse_fw_sync on BS_PRE_DEVICE entry. This was being done later in the boot process to ensure that the memory training parameters are written back to SPI flash before performing a reset for CSE RW jump. With the recent changes in CB:44196 ("mrc_cache: Update mrc_cache data in romstage"), MRC cache is updated right away in romstage. So, CSE RW jump can be performed in BS_PRE_DEVICE phase.
Signed-off-by: Furquan Shaikh furquan@google.com Change-Id: I947a40cd9776342d2067c9d5a366358917466d58 --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 0 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/48130/1
diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 9c498b5..9011593 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -809,12 +809,4 @@ } }
-#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_JASPERLAKE) -/* - * This needs to happen after the MRC cache write to avoid a 2nd - * memory training sequence. - */ -BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, cse_fw_sync, NULL); -#else BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, cse_fw_sync, NULL); -#endif
Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48130 )
Change subject: soc/intel/common/cse: Perform cse_fw_sync on BS_PRE_DEVICE entry ......................................................................
Patch Set 1: Code-Review+1
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48130 )
Change subject: soc/intel/common/cse: Perform cse_fw_sync on BS_PRE_DEVICE entry ......................................................................
Patch Set 1: Code-Review+2
Jamie Ryu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48130 )
Change subject: soc/intel/common/cse: Perform cse_fw_sync on BS_PRE_DEVICE entry ......................................................................
Patch Set 1: Code-Review+1
Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48130 )
Change subject: soc/intel/common/cse: Perform cse_fw_sync on BS_PRE_DEVICE entry ......................................................................
soc/intel/common/cse: Perform cse_fw_sync on BS_PRE_DEVICE entry
This change drops the special check added for TGL/JSL platforms and performs cse_fw_sync on BS_PRE_DEVICE entry. This was being done later in the boot process to ensure that the memory training parameters are written back to SPI flash before performing a reset for CSE RW jump. With the recent changes in CB:44196 ("mrc_cache: Update mrc_cache data in romstage"), MRC cache is updated right away in romstage. So, CSE RW jump can be performed in BS_PRE_DEVICE phase.
Signed-off-by: Furquan Shaikh furquan@google.com Change-Id: I947a40cd9776342d2067c9d5a366358917466d58 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48130 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Sridhar Siricilla sridhar.siricilla@intel.com Reviewed-by: Duncan Laurie dlaurie@chromium.org Reviewed-by: Jamie Ryu jamie.m.ryu@intel.com --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 0 insertions(+), 8 deletions(-)
Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved Sridhar Siricilla: Looks good to me, but someone else must approve Jamie Ryu: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 9c498b5..9011593 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -809,12 +809,4 @@ } }
-#if CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(SOC_INTEL_JASPERLAKE) -/* - * This needs to happen after the MRC cache write to avoid a 2nd - * memory training sequence. - */ -BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, cse_fw_sync, NULL); -#else BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, cse_fw_sync, NULL); -#endif
-
Duncan Laurie (Code Review) -
Furquan Shaikh (Code Review)
-
Jamie Ryu (Code Review)
-
Sridhar Siricilla (Code Review)