Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47969 )
Change subject: cpu/x86: Link entry32.inc ......................................................................
cpu/x86: Link entry32.inc
TBD: Address SPDX license header mismatch
Change-Id: Ib475f40f950f8cc54f0e3c50a80970ba3d2b628f Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/arch/x86/Makefile.inc D src/cpu/x86/32bit/entry32.inc M src/cpu/x86/Makefile.inc R src/cpu/x86/entry32.S 4 files changed, 30 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/47969/1
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 3727165..58de291 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -101,8 +101,6 @@ bootblock-y += gdt_init.S bootblock-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c
-bootblock-y += bootblock_crt0.S - ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) $(eval $(call early_x86_stage,bootblock,elf32-i386)) else diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc deleted file mode 100644 index b28fa2f..0000000 --- a/src/cpu/x86/32bit/entry32.inc +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* For starting coreboot in protected mode */ - -#include <arch/rom_segs.h> -#include <cpu/x86/post_code.h> - - .code32 -/* - * When we come here we are in protected mode. - * NOTE aligned to 4 so that we are sure that the prefetch - * cache will be reloaded. - */ - .align 4 - -.globl __protected_start -__protected_start: - /* Save the BIST value */ - movl %eax, %ebp - -#if !CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES) - post_code(POST_ENTER_PROTECTED_MODE) -#endif - - movw $ROM_DATA_SEG, %ax - movw %ax, %ds - movw %ax, %es - movw %ax, %ss - movw %ax, %fs - movw %ax, %gs - - /* Restore the BIST value to %eax */ - movl %ebp, %eax diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index f1bca0e..33a65e7 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -5,6 +5,7 @@
subdirs-$(CONFIG_CPU_INTEL_COMMON_SMM) += ../intel/smm
+bootblock-y += entry32.S bootblock-y += entry16.S bootblock-y += reset16.S
diff --git a/src/arch/x86/bootblock_crt0.S b/src/cpu/x86/entry32.S similarity index 61% rename from src/arch/x86/bootblock_crt0.S rename to src/cpu/x86/entry32.S index d151feb..d428fd4 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/cpu/x86/entry32.S @@ -1,4 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* For starting coreboot in protected mode */ + /* * This is the modern bootblock. It prepares the system for C environment runtime * setup. The actual setup is done by hardware-specific code. @@ -8,15 +11,38 @@ * */
+#include <arch/rom_segs.h> #include <cpu/x86/cr.h> +#include <cpu/x86/post_code.h>
.section ".init", "ax", @progbits
+ .code32 /* - * Include the old code for reset vector and protected mode entry. That code has - * withstood the test of time. + * When we come here we are in protected mode. + * NOTE aligned to 4 so that we are sure that the prefetch + * cache will be reloaded. */ -#include <cpu/x86/32bit/entry32.inc> + .align 4 + +.globl __protected_start +__protected_start: + /* Save the BIST value */ + movl %eax, %ebp + +#if !CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES) + post_code(POST_ENTER_PROTECTED_MODE) +#endif + + movw $ROM_DATA_SEG, %ax + movw %ax, %ds + movw %ax, %es + movw %ax, %ss + movw %ax, %fs + movw %ax, %gs + + /* Restore the BIST value to %eax */ + movl %ebp, %eax
#if CONFIG(BOOTBLOCK_DEBUG_SPINLOOP)
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47969
to look at the new patch set (#4).
Change subject: cpu/x86: Link entry32.inc ......................................................................
cpu/x86: Link entry32.inc
TBD: Address SPDX license header mismatch
Change-Id: Ib475f40f950f8cc54f0e3c50a80970ba3d2b628f Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/arch/x86/Makefile.inc D src/cpu/x86/32bit/entry32.inc M src/cpu/x86/Makefile.inc R src/cpu/x86/entry32.S 4 files changed, 30 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/47969/4
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47969 )
Change subject: cpu/x86: Link entry32.inc ......................................................................
Patch Set 5:
It looks like it should work. Do we have any opinions on doing away with "crt0"? Do any boards currently report anything for "make printcrt0s"? I did a quick spot check and didn't come up with anything.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47969 )
Change subject: cpu/x86: Link entry32.inc ......................................................................
Patch Set 5:
Patch Set 5:
It looks like it should work. Do we have any opinions on doing away with "crt0"? Do any boards currently report anything for "make printcrt0s"? I did a quick spot check and didn't come up with anything.
Hmm.. looks like cpu_incs-y has become obsolete in favor of linking .S files independently.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47969
to look at the new patch set (#6).
Change subject: cpu/x86: Link entry32.inc ......................................................................
cpu/x86: Link entry32.inc
TBD: Address SPDX license header mismatch
Change-Id: Ib475f40f950f8cc54f0e3c50a80970ba3d2b628f Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/arch/x86/Makefile.inc D src/cpu/x86/32bit/entry32.inc M src/cpu/x86/Makefile.inc R src/cpu/x86/entry32.S 4 files changed, 30 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/47969/6
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47969 )
Change subject: cpu/x86: Link entry32.inc ......................................................................
Patch Set 8: Code-Review+2
Attention is currently required from: Kyösti Mälkki. ron minnich has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47969 )
Change subject: cpu/x86: Link entry32.inc ......................................................................
Patch Set 9: Code-Review+2
(1 comment)
Patchset:
PS9: When the license was written the idea of a "later than GPL V2" was not even a concept. I think GPL 2 or later is fine.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Arthur Heymans, ron minnich,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47969
to look at the new patch set (#10).
Change subject: cpu/x86: Link entry32.inc ......................................................................
cpu/x86: Link entry32.inc
Change-Id: Ib475f40f950f8cc54f0e3c50a80970ba3d2b628f Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/arch/x86/Makefile.inc D src/cpu/x86/32bit/entry32.inc M src/cpu/x86/Makefile.inc R src/cpu/x86/entry32.S 4 files changed, 30 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/47969/10
Attention is currently required from: Kyösti Mälkki. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47969 )
Change subject: cpu/x86: Link entry32.inc ......................................................................
Patch Set 10: Code-Review+2
Attention is currently required from: Kyösti Mälkki. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47969 )
Change subject: cpu/x86: Link entry32.inc ......................................................................
Patch Set 10: Code-Review+2
Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47969 )
Change subject: cpu/x86: Link entry32.inc ......................................................................
cpu/x86: Link entry32.inc
Change-Id: Ib475f40f950f8cc54f0e3c50a80970ba3d2b628f Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/47969 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Raul Rangel rrangel@chromium.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/arch/x86/Makefile.inc D src/cpu/x86/32bit/entry32.inc M src/cpu/x86/Makefile.inc R src/cpu/x86/entry32.S 4 files changed, 30 insertions(+), 38 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Raul Rangel: Looks good to me, approved
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index cfefec6..7dea2ce 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -85,8 +85,6 @@
$(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h
-bootblock-y += bootblock_crt0.S - ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) $(eval $(call early_x86_stage,bootblock,elf32-i386)) else diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc deleted file mode 100644 index b28fa2f..0000000 --- a/src/cpu/x86/32bit/entry32.inc +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* For starting coreboot in protected mode */ - -#include <arch/rom_segs.h> -#include <cpu/x86/post_code.h> - - .code32 -/* - * When we come here we are in protected mode. - * NOTE aligned to 4 so that we are sure that the prefetch - * cache will be reloaded. - */ - .align 4 - -.globl __protected_start -__protected_start: - /* Save the BIST value */ - movl %eax, %ebp - -#if !CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES) - post_code(POST_ENTER_PROTECTED_MODE) -#endif - - movw $ROM_DATA_SEG, %ax - movw %ax, %ds - movw %ax, %es - movw %ax, %ss - movw %ax, %fs - movw %ax, %gs - - /* Restore the BIST value to %eax */ - movl %ebp, %eax diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 9112ddb..f1d41bd 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -8,6 +8,7 @@
subdirs-$(CONFIG_CPU_INTEL_COMMON_SMM) += ../intel/smm
+bootblock-y += entry32.S bootblock-y += entry16.S bootblock-y += reset16.S
diff --git a/src/arch/x86/bootblock_crt0.S b/src/cpu/x86/entry32.S similarity index 61% rename from src/arch/x86/bootblock_crt0.S rename to src/cpu/x86/entry32.S index 16daed1..32f61ad 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/cpu/x86/entry32.S @@ -1,4 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* For starting coreboot in protected mode */ + /* * This is the modern bootblock. It prepares the system for C environment runtime * setup. The actual setup is done by hardware-specific code. @@ -8,15 +11,38 @@ * */
+#include <arch/rom_segs.h> #include <cpu/x86/cr.h> +#include <cpu/x86/post_code.h>
.section .init, "ax", @progbits
+ .code32 /* - * Include the old code for reset vector and protected mode entry. That code has - * withstood the test of time. + * When we come here we are in protected mode. + * NOTE aligned to 4 so that we are sure that the prefetch + * cache will be reloaded. */ -#include <cpu/x86/32bit/entry32.inc> + .align 4 + +.globl __protected_start +__protected_start: + /* Save the BIST value */ + movl %eax, %ebp + +#if !CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES) + post_code(POST_ENTER_PROTECTED_MODE) +#endif + + movw $ROM_DATA_SEG, %ax + movw %ax, %ds + movw %ax, %es + movw %ax, %ss + movw %ax, %fs + movw %ax, %gs + + /* Restore the BIST value to %eax */ + movl %ebp, %eax
#if CONFIG(BOOTBLOCK_DEBUG_SPINLOOP)
-
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Kyösti Mälkki (Code Review)
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