Change in coreboot[master]: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3444
Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47555 )
Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3444 ......................................................................
vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3444
Update FSP headers for Tiger Lake platform generated based on FSP version 3444. Previous version was 3425.
BUG=b:173160613 BRANCH=none TEST=build and boot delbin
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: I9e5de1617d00cd7543d4de1660f448e2fe220b0a --- M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h 2 files changed, 6 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/47555/1
diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h index 6038b13..35cc43b 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h @@ -2498,7 +2498,7 @@
/** Offset 0x091C - Reserved **/ - UINT8 Reserved45[36]; + UINT8 Reserved45[44]; } FSP_M_CONFIG;
/** Fsp M UPD Configuration @@ -2517,11 +2517,11 @@ **/ FSP_M_CONFIG FspmConfig;
-/** Offset 0x0940 +/** Offset 0x0948 **/ UINT8 UnusedUpdSpace27[6];
-/** Offset 0x0946 +/** Offset 0x094E **/ UINT16 UpdTerminator; } FSPM_UPD; diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h index b7ef000..276ac79 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h @@ -1058,10 +1058,10 @@ UINT16 ITbtDmaLtr[2];
/** Offset 0x04E2 - Enable/Disable CrashLog - Enable(Default): Enable CPU CrashLog, Disable: Disable CPU CrashLog + Deprecated. Move to PreMem $EN_DIS **/ - UINT8 CpuCrashLogEnable; + UINT8 DeprecatedCpuCrashLogEnable;
/** Offset 0x04E3 - Enable/Disable PTM This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports @@ -2838,7 +2838,7 @@ /** Offset 0x0B95 - Configuration for boot TDP selection Deprecated. Move to premem. **/ - UINT8 ConfigTdpLevel; + UINT8 DeprecatedConfigTdpLevel;
/** Offset 0x0B96 - Max P-State Ratio Max P-State Ratio, Valid Range 0 to 0x7F
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47555 )
Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3444 ......................................................................
Patch Set 1: Code-Review+1
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47555 )
Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3444 ......................................................................
Patch Set 1: Code-Review+1
Dossym Nurmukhanov has uploaded a new patch set (#2) to the change originally created by Srinidhi N Kaushik. ( https://review.coreboot.org/c/coreboot/+/47555 )
Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3444 ......................................................................
vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3444
Update FSP headers for Tiger Lake platform generated based on FSP version 3444. Previous version was 3425.
BUG=b:173160613 BRANCH=none TEST=build and boot delbin
Cq-Depend:chrome-internal:3403586, chrome-internal:3403392 Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: I9e5de1617d00cd7543d4de1660f448e2fe220b0a --- M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h 2 files changed, 6 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/47555/2
Dossym Nurmukhanov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47555 )
Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3444 ......................................................................
Patch Set 2: Code-Review+2
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47555 )
Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3444 ......................................................................
Patch Set 2: Code-Review+2
Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47555 )
Change subject: vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3444 ......................................................................
vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3444
Update FSP headers for Tiger Lake platform generated based on FSP version 3444. Previous version was 3425.
BUG=b:173160613 BRANCH=none TEST=build and boot delbin
Cq-Depend:chrome-internal:3403586, chrome-internal:3403392 Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: I9e5de1617d00cd7543d4de1660f448e2fe220b0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/47555 Reviewed-by: Dossym Nurmukhanov dossym@google.com Reviewed-by: Nick Vaccaro nvaccaro@google.com Reviewed-by: Wonkyu Kim wonkyu.kim@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h 2 files changed, 6 insertions(+), 6 deletions(-)
Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Srinidhi N Kaushik: Looks good to me, but someone else must approve Wonkyu Kim: Looks good to me, but someone else must approve Dossym Nurmukhanov: Looks good to me, approved
diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h index 6038b13..35cc43b 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h @@ -2498,7 +2498,7 @@
/** Offset 0x091C - Reserved **/ - UINT8 Reserved45[36]; + UINT8 Reserved45[44]; } FSP_M_CONFIG;
/** Fsp M UPD Configuration @@ -2517,11 +2517,11 @@ **/ FSP_M_CONFIG FspmConfig;
-/** Offset 0x0940 +/** Offset 0x0948 **/ UINT8 UnusedUpdSpace27[6];
-/** Offset 0x0946 +/** Offset 0x094E **/ UINT16 UpdTerminator; } FSPM_UPD; diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h index b7ef000..276ac79 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h @@ -1058,10 +1058,10 @@ UINT16 ITbtDmaLtr[2];
/** Offset 0x04E2 - Enable/Disable CrashLog - Enable(Default): Enable CPU CrashLog, Disable: Disable CPU CrashLog + Deprecated. Move to PreMem $EN_DIS **/ - UINT8 CpuCrashLogEnable; + UINT8 DeprecatedCpuCrashLogEnable;
/** Offset 0x04E3 - Enable/Disable PTM This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports @@ -2838,7 +2838,7 @@ /** Offset 0x0B95 - Configuration for boot TDP selection Deprecated. Move to premem. **/ - UINT8 ConfigTdpLevel; + UINT8 DeprecatedConfigTdpLevel;
/** Offset 0x0B96 - Max P-State Ratio Max P-State Ratio, Valid Range 0 to 0x7F
-
Dossym Nurmukhanov (Code Review) -
Nick Vaccaro (Code Review)
-
Srinidhi N Kaushik (Code Review)
-
Wonkyu Kim (Code Review)