Change in coreboot[master]: soc/mediatek/mt8186: Enable DCM

[Rex-BC Chen (Code Review)]

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59338 )

Change subject: soc/mediatek/mt8186: Enable DCM
......................................................................

soc/mediatek/mt8186: Enable DCM

DCM (dynamic clock management) can dynamically slow down or gate clocks
during CPU or bus idle. Enable DCM settings on the MT8186 platform.

TEST=build pass and check register ok
BUG=b:202871018

Signed-off-by: Edward-JW Yang 
Change-Id: I82add5ae629d59f7d6773e26ac9cba9d54ab8caf
---
M src/soc/mediatek/mt8186/include/soc/pll.h
M src/soc/mediatek/mt8186/pll.c
2 files changed, 82 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/59338/1

diff --git a/src/soc/mediatek/mt8186/include/soc/pll.h b/src/soc/mediatek/mt8186/include/soc/pll.h
index 4638f50a..c744754 100644
--- a/src/soc/mediatek/mt8186/include/soc/pll.h
+++ b/src/soc/mediatek/mt8186/include/soc/pll.h
@@ -507,4 +507,61 @@
 DEFINE_BITFIELD(CLK_MISC_CFG_0_METER_DIV, 31, 24)
 DEFINE_BITFIELD(CLK26CALI_0_ENABLE, 12, 12)
 DEFINE_BITFIELD(CLK26CALI_0_TRIGGER, 4, 4)
+
+enum {
+	INFRACFG_AO_AUDIO_BUS_REG0_MASK = (0x1 << 29),
+	INFRACFG_AO_AUDIO_BUS_REG0_ON = (0x1 << 29),
+	INFRACFG_AO_ICUSB_BUS_REG0_MASK = (0x1 << 28),
+	INFRACFG_AO_ICUSB_BUS_REG0_ON = (0x1 << 28),
+	INFRACFG_AO_INFRA_BUS_REG0_MASK = (0x1 << 0) |
+					  (0x1 << 1) |
+					  (0x1 << 2) |
+					  (0x1 << 3) |
+					  (0x1 << 4) |
+					  (0x1f << 5) |
+					  (0x1f << 10) |
+					  (0x1 << 20) |
+					  (0x1 << 21) |
+					  (0x1 << 22) |
+					  (0x1 << 23) |
+					  (0x1 << 30),
+	INFRACFG_AO_INFRA_BUS_REG0_ON = (0x1 << 0) |
+					(0x1 << 1) |
+					(0x0 << 2) |
+					(0x0 << 3) |
+					(0x0 << 4) |
+					(0x10 << 5) |
+					(0x1 << 10) |
+					(0x1 << 20) |
+					(0x1 << 21) |
+					(0x1 << 22) |
+					(0x1 << 23) |
+					(0x1 << 30),
+	INFRACFG_AO_P2P_RX_CLK_REG0_MASK = (0x1 << 0) | (0x1 << 5),
+	INFRACFG_AO_P2P_RX_CLK_REG0_ON = (0x0 << 0) | (0x1 << 5),
+	INFRACFG_AO_PERI_BUS_REG0_MASK = (0x1 << 0) |
+					 (0x1 << 1) |
+					 (0x1 << 3) |
+					 (0x1 << 4) |
+					 (0x1f << 5) |
+					 (0x1f << 10) |
+					 (0x1f << 15) |
+					 (0x1 << 20) |
+					 (0x1 << 21) |
+					 (0x1 << 22) |
+					 (0x1f << 23) |
+					 (0x1 << 31),
+	INFRACFG_AO_PERI_BUS_REG0_ON = (0x1 << 0) |
+				       (0x1 << 1) |
+				       (0x0 << 3) |
+				       (0x0 << 4) |
+				       (0x1f << 5) |
+				       (0x0 << 10) |
+				       (0x1f << 15) |
+				       (0x1 << 20) |
+				       (0x1 << 21) |
+				       (0x1 << 22) |
+				       (0x0 << 23) |
+				       (0x1 << 31),
+};
 #endif /* SOC_MEDIATEK_MT8186_PLL_H */
diff --git a/src/soc/mediatek/mt8186/pll.c b/src/soc/mediatek/mt8186/pll.c
index 7f9d748..7d10e9c 100644
--- a/src/soc/mediatek/mt8186/pll.c
+++ b/src/soc/mediatek/mt8186/pll.c
@@ -436,6 +436,31 @@
    write32(&mt8186_infracfg_ao->infra_bus_dcm_ctrl, 0x805f0603);
    write32(&mt8186_infracfg_ao->peri_bus_dcm_ctrl, 0xb07f0603);

+	/* dcm_infracfg_ao_audio_bus */
+	clrsetbits32(&mt8186_infracfg_ao->peri_bus_dcm_ctrl,
+		     INFRACFG_AO_AUDIO_BUS_REG0_MASK,
+		     INFRACFG_AO_AUDIO_BUS_REG0_ON);
+
+	/* dcm_infracfg_ao_icusb_bus */
+	clrsetbits32(&mt8186_infracfg_ao->peri_bus_dcm_ctrl,
+		     INFRACFG_AO_ICUSB_BUS_REG0_MASK,
+		     INFRACFG_AO_ICUSB_BUS_REG0_ON);
+
+	/* dcm_infracfg_ao_infra_bus */
+	clrsetbits32(&mt8186_infracfg_ao->infra_bus_dcm_ctrl,
+		     INFRACFG_AO_INFRA_BUS_REG0_MASK,
+		     INFRACFG_AO_INFRA_BUS_REG0_ON);
+
+	/* dcm_infracfg_ao_p2p_rx_clk */
+	clrsetbits32(&mt8186_infracfg_ao->p2p_rx_clk_on,
+		     INFRACFG_AO_P2P_RX_CLK_REG0_MASK,
+		     INFRACFG_AO_P2P_RX_CLK_REG0_ON);
+
+	/* dcm_infracfg_ao_peri_bus */
+	clrsetbits32(&mt8186_infracfg_ao->peri_bus_dcm_ctrl,
+		     INFRACFG_AO_PERI_BUS_REG0_MASK,
+		     INFRACFG_AO_PERI_BUS_REG0_ON);
+
    for (i = 0; i < ARRAY_SIZE(mux_sels); i++)
    	mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);