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Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74430 )
Change subject: ACPI: Obsolete FADT p_lvl2_lat and p_lvl3_lat fields ......................................................................
ACPI: Obsolete FADT p_lvl2_lat and p_lvl3_lat fields
After the obsoletion of Processor() it is necessary to provide _CST package to define P_BLK IO address for C2/C3 transitions. Therefore, the latency values from _CST will always replace those in FADT.
Change-Id: I3230be719659fe9cdf9ed6ae73bc91b05093ab97 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/acpi/acpi.c M src/soc/amd/cezanne/acpi.c M src/soc/amd/glinda/acpi.c M src/soc/amd/mendocino/acpi.c M src/soc/amd/phoenix/acpi.c M src/soc/amd/picasso/acpi.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/xeon_sp/spr/soc_acpi.c M src/southbridge/amd/pi/hudson/fadt.c M src/southbridge/intel/bd82x6x/fadt.c M src/southbridge/intel/i82371eb/fadt.c M src/southbridge/intel/ibexpeak/fadt.c M src/southbridge/intel/lynxpoint/fadt.c 13 files changed, 19 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/74430/1
diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index de5abe0..88e503e 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1682,6 +1682,10 @@ /* should be 0 ACPI 3.0 */ fadt->reserved = 0;
+ /* P_LVLx not used as CPU _CST will override them. */ + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; + fadt->preferred_pm_profile = acpi_get_preferred_pm_profile();
if (CONFIG(USE_PC_CMOS_ALTCENTURY)) diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index b8ac827..7b8393b 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -72,10 +72,6 @@
fill_fadt_extended_pm_regs(fadt);
- /* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are - overridden by the _CST packages in the processor devices. */ - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->day_alrm = RTC_DATE_ALARM; fadt->century = RTC_ALT_CENTURY; fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */ diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c index 49fb658..5eae366 100644 --- a/src/soc/amd/glinda/acpi.c +++ b/src/soc/amd/glinda/acpi.c @@ -75,10 +75,6 @@
fill_fadt_extended_pm_regs(fadt);
- /* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are - overridden by the _CST packages in the processor devices. */ - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->day_alrm = RTC_DATE_ALARM; fadt->century = RTC_ALT_CENTURY; fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */ diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c index 83b24ec..6228777 100644 --- a/src/soc/amd/mendocino/acpi.c +++ b/src/soc/amd/mendocino/acpi.c @@ -74,10 +74,6 @@
fill_fadt_extended_pm_regs(fadt);
- /* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are - overridden by the _CST packages in the processor devices. */ - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->day_alrm = RTC_DATE_ALARM; fadt->century = RTC_ALT_CENTURY; fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */ diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c index 8e90d44..514ed0e 100644 --- a/src/soc/amd/phoenix/acpi.c +++ b/src/soc/amd/phoenix/acpi.c @@ -75,10 +75,6 @@
fill_fadt_extended_pm_regs(fadt);
- /* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are - overridden by the _CST packages in the processor devices. */ - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->day_alrm = RTC_DATE_ALARM; fadt->century = RTC_ALT_CENTURY; fadt->iapc_boot_arch = cfg->common_config.fadt_boot_arch; /* legacy free default */ diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index a6f1ebd..1a995be 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -80,10 +80,6 @@
fill_fadt_extended_pm_regs(fadt);
- /* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are - overridden by the _CST packages in the processor devices. */ - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->day_alrm = RTC_DATE_ALARM; fadt->iapc_boot_arch = cfg->fadt_boot_arch; /* legacy free default */ fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */ diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index caa6496..dfa7d61 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -74,10 +74,6 @@
fill_fadt_extended_pm_regs(fadt);
- /* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are - overridden by the _CST packages in the PSTATE SSDT. */ - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */ fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ fadt->day_alrm = RTC_DATE_ALARM; diff --git a/src/soc/intel/xeon_sp/spr/soc_acpi.c b/src/soc/intel/xeon_sp/spr/soc_acpi.c index c609f4f..0233c37 100644 --- a/src/soc/intel/xeon_sp/spr/soc_acpi.c +++ b/src/soc/intel/xeon_sp/spr/soc_acpi.c @@ -48,8 +48,6 @@ fadt->pm2_cnt_blk = pmbase + PM2_CNT; fadt->pm2_cnt_len = 1; fadt->gpe0_blk = pmbase + 0x60; - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->duty_offset = 1;
fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c index 4989d6b..fe286fe 100644 --- a/src/southbridge/amd/pi/hudson/fadt.c +++ b/src/southbridge/amd/pi/hudson/fadt.c @@ -44,8 +44,6 @@ fadt->pm_tmr_len = 4; /* 32 bits */ fadt->gpe0_blk_len = 8; /* 64 bits */
- fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */ fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ fadt->day_alrm = 0; /* 0x7d these have to be */ diff --git a/src/southbridge/intel/bd82x6x/fadt.c b/src/southbridge/intel/bd82x6x/fadt.c index be315af..a9e7a36 100644 --- a/src/southbridge/intel/bd82x6x/fadt.c +++ b/src/southbridge/intel/bd82x6x/fadt.c @@ -31,9 +31,6 @@ fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 16; - /* P_LVLx not used */ - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; /* P_CNT not supported */ fadt->duty_offset = 0; fadt->duty_width = 0; diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index fc3258a..681d09c 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -36,8 +36,6 @@ fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 4;
- fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */ fadt->duty_width = 3; /* this width is in bits */ fadt->day_alrm = 0x0d; /* rtc CMOS RAM offset */ diff --git a/src/southbridge/intel/ibexpeak/fadt.c b/src/southbridge/intel/ibexpeak/fadt.c index 9921b4d..d6084ee 100644 --- a/src/southbridge/intel/ibexpeak/fadt.c +++ b/src/southbridge/intel/ibexpeak/fadt.c @@ -31,9 +31,6 @@ fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; fadt->gpe0_blk_len = 16; - /* P_LVLx not used */ - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; /* P_CNT not supported */ fadt->duty_offset = 0; fadt->duty_width = 0; diff --git a/src/southbridge/intel/lynxpoint/fadt.c b/src/southbridge/intel/lynxpoint/fadt.c index fc08f01..ba9439c 100644 --- a/src/southbridge/intel/lynxpoint/fadt.c +++ b/src/southbridge/intel/lynxpoint/fadt.c @@ -44,9 +44,6 @@ else fadt->gpe0_blk_len = 2 * 8;
- /* P_LVLx not used */ - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->duty_offset = 0; fadt->duty_width = 0; fadt->day_alrm = 0xd;
-
Kyösti Mälkki (Code Review)