Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43528 )
Change subject: mb/google/volteer: Update DPTF with temp sensor 3 ......................................................................
mb/google/volteer: Update DPTF with temp sensor 3
While the DPTF refactor was in progress, TSR3 was added to volteer's dptf.asl file, and I forgot to update the devicetree with TSR3 as well. This patch fixes that.
BUG=b:149722146 TEST=boot volteer, dump SSDT & DSDT, verify TSR3._STA returns 0xF
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: I71bc798492ec45bb1e2f8d779e6829db52ef4499 --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/43528/1
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index f0bb25b..b8f6f24 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -311,18 +311,26 @@ TEMP_PCT(45, 56), TEMP_PCT(42, 46), TEMP_PCT(39, 36),}}" + register "policies.active[4]" = "{.target=DPTF_TEMP_SENSOR_3, + .thresholds={TEMP_PCT(50, 90), + TEMP_PCT(47, 69), + TEMP_PCT(45, 56), + TEMP_PCT(42, 46), + TEMP_PCT(39, 36),}}"
## Passive Policy register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)" register "policies.passive[2]" = "DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 65, 6000)" register "policies.passive[3]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 65, 6000)" + register "policies.passive[4]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 65, 6000)"
## Critical Policy register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)" register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 75, SHUTDOWN)" register "policies.critical[3]" = "DPTF_CRITICAL(TEMP_SENSOR_2, 75, SHUTDOWN)" + register "policies.critical[4]" = "DPTF_CRITICAL(TEMP_SENSOR_3, 75, SHUTDOWN)"
## Power Limits Control # 10-15W PL1 in 200mW increments, avg over 28-32s interval
Deepika Punyamurtula has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43528 )
Change subject: mb/google/volteer: Update DPTF with temp sensor 3 ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43528/1/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43528/1/src/mainboard/google/voltee... PS1, Line 324: register "policies.passive[2]" = "DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 65, 6000)" Hi Tim, Can you also please update the target for the Charger to TEMP_SENSOR_0 in the Passive table (swap temp_sensor_0 and 1)? temp_sensor_0 is the charging inductor sensor on Volteer. Please see https://review.coreboot.org/c/coreboot/+/42232 for your reference. Thank you.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43528 )
Change subject: mb/google/volteer: Update DPTF with temp sensor 3 ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43528/1/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43528/1/src/mainboard/google/voltee... PS1, Line 324: register "policies.passive[2]" = "DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 65, 6000)"
Hi Tim, Can you also please update the target for the Charger to TEMP_SENSOR_0 in the Passive table […]
Thank you for catching that, we'll get this right eventually! Will fix in next patchset.
Hello build bot (Jenkins), Deepika Punyamurtula, Caveh Jalali, Duncan Laurie, Sumeet R Pawnikar, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43528
to look at the new patch set (#2).
Change subject: mb/google/volteer: Update DPTF with temp sensor 3 ......................................................................
mb/google/volteer: Update DPTF with temp sensor 3
While the DPTF refactor was in progress, TSR3 was added to volteer's dptf.asl file, and I forgot to update the devicetree with TSR3 as well. Also missed a swap in the passive policies of TSR0 and TSR1. This patch fixes those.
BUG=b:149722146 TEST=boot volteer, dump SSDT & DSDT, verify TSR3._STA returns 0xF
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: I71bc798492ec45bb1e2f8d779e6829db52ef4499 --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 12 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/43528/2
Deepika Punyamurtula has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43528 )
Change subject: mb/google/volteer: Update DPTF with temp sensor 3 ......................................................................
Patch Set 2: Code-Review+1
Thanks Tim !
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43528 )
Change subject: mb/google/volteer: Update DPTF with temp sensor 3 ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43528/2/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43528/2/src/mainboard/google/voltee... PS2, Line 323: 60000 one minute seems like an awful long time here.
Deepika Punyamurtula has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43528 )
Change subject: mb/google/volteer: Update DPTF with temp sensor 3 ......................................................................
Patch Set 2: -Code-Review
(1 comment)
https://review.coreboot.org/c/coreboot/+/43528/2/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43528/2/src/mainboard/google/voltee... PS2, Line 323: register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 60000)" Yeah, if the values are in milliseconds looks like these should be reduced by a factor of 10
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43528 )
Change subject: mb/google/volteer: Update DPTF with temp sensor 3 ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43528/2/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43528/2/src/mainboard/google/voltee... PS2, Line 323: 60000
one minute seems like an awful long time here.
Ugh, these units are giving me a hard time 😞
https://review.coreboot.org/c/coreboot/+/43528/2/src/mainboard/google/voltee... PS2, Line 323: register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 60000)"
Yeah, if the values are in milliseconds looks like these should be reduced by a factor of 10
Yep, will fix.
Hello build bot (Jenkins), Deepika Punyamurtula, Caveh Jalali, Duncan Laurie, Sumeet R Pawnikar, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43528
to look at the new patch set (#3).
Change subject: mb/google/volteer: Update DPTF with temp sensor 3 ......................................................................
mb/google/volteer: Update DPTF with temp sensor 3
While the DPTF refactor was in progress, TSR3 was added to volteer's dptf.asl file, and I forgot to update the devicetree with TSR3 as well. Also missed a swap in the passive policies of TSR0 and TSR1. This patch fixes those.
BUG=b:149722146 TEST=boot volteer, dump SSDT & DSDT, verify TSR3._STA returns 0xF
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: I71bc798492ec45bb1e2f8d779e6829db52ef4499 --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 10 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/43528/3
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43528 )
Change subject: mb/google/volteer: Update DPTF with temp sensor 3 ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43528/2/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43528/2/src/mainboard/google/voltee... PS2, Line 323: register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 60000)"
Yep, will fix.
Done
https://review.coreboot.org/c/coreboot/+/43528/2/src/mainboard/google/voltee... PS2, Line 323: 60000
Ugh, these units are giving me a hard time 😞
Done
Deepika Punyamurtula has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43528 )
Change subject: mb/google/volteer: Update DPTF with temp sensor 3 ......................................................................
Patch Set 3: Code-Review+1
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43528 )
Change subject: mb/google/volteer: Update DPTF with temp sensor 3 ......................................................................
Patch Set 3: Code-Review+2
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43528 )
Change subject: mb/google/volteer: Update DPTF with temp sensor 3 ......................................................................
Patch Set 3: Code-Review+1
Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43528 )
Change subject: mb/google/volteer: Update DPTF with temp sensor 3 ......................................................................
mb/google/volteer: Update DPTF with temp sensor 3
While the DPTF refactor was in progress, TSR3 was added to volteer's dptf.asl file, and I forgot to update the devicetree with TSR3 as well. Also missed a swap in the passive policies of TSR0 and TSR1. This patch fixes those.
BUG=b:149722146 TEST=boot volteer, dump SSDT & DSDT, verify TSR3._STA returns 0xF
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: I71bc798492ec45bb1e2f8d779e6829db52ef4499 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43528 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Deepika Punyamurtula deepika.punyamurtula@intel.com Reviewed-by: Nick Vaccaro nvaccaro@google.com Reviewed-by: Caveh Jalali caveh@chromium.org --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 10 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Caveh Jalali: Looks good to me, but someone else must approve Deepika Punyamurtula: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index f0bb25b..e0d3bea 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -311,18 +311,26 @@ TEMP_PCT(45, 56), TEMP_PCT(42, 46), TEMP_PCT(39, 36),}}" + register "policies.active[4]" = "{.target=DPTF_TEMP_SENSOR_3, + .thresholds={TEMP_PCT(50, 90), + TEMP_PCT(47, 69), + TEMP_PCT(45, 56), + TEMP_PCT(42, 46), + TEMP_PCT(39, 36),}}"
## Passive Policy register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)" - register "policies.passive[2]" = "DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 65, 6000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 6000)" + register "policies.passive[2]" = "DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 65, 6000)" register "policies.passive[3]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 65, 6000)" + register "policies.passive[4]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 65, 6000)"
## Critical Policy register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)" register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 75, SHUTDOWN)" register "policies.critical[3]" = "DPTF_CRITICAL(TEMP_SENSOR_2, 75, SHUTDOWN)" + register "policies.critical[4]" = "DPTF_CRITICAL(TEMP_SENSOR_3, 75, SHUTDOWN)"
## Power Limits Control # 10-15W PL1 in 200mW increments, avg over 28-32s interval
-
Caveh Jalali (Code Review) -
Deepika Punyamurtula (Code Review)
-
Nick Vaccaro (Code Review)
-
Tim Wawrzynczak (Code Review)