Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62587 )
Change subject: soc/intel/common: Use heci_reset() in the CSE TX and RX flows ......................................................................
soc/intel/common: Use heci_reset() in the CSE TX and RX flows
The patch implements error handling as per the ME BWG guide. The BWG recommends HECI interface reset if there is a timeout or malformed response is received from the CSE. Also, the patch triggers HECI interface reset if the CSE link state is not ready in the heci_send() API.
TEST=Verify HECI Interface reset in the simulated error scenarios.
Signed-off-by: Sridhar Siricilla sridhar.siricilla@intel.com Change-Id: I3e4a97800cbc5d95b8fd259e6e34a32fc82d8563 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62587 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 6 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 810973b..bbd8afc 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -458,6 +458,8 @@ return CSE_TX_RX_SUCCESS; }
+ printk(BIOS_DEBUG, "HECI: Trigger HECI reset\n"); + heci_reset(); return CSE_TX_ERR_CSE_NOT_READY; }
@@ -548,7 +550,7 @@ ret = recv_one_message(&hdr, p, left, &received); if (ret) { printk(BIOS_ERR, "HECI: Failed to receive!\n"); - return ret; + goto CSE_RX_ERR_HANDLE; } left -= received; p += received; @@ -563,6 +565,9 @@ } }
+CSE_RX_ERR_HANDLE: + printk(BIOS_DEBUG, "HECI: Trigger HECI Reset\n"); + heci_reset(); return CSE_RX_ERR_CSE_NOT_READY; }
4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one.