Change in coreboot[master]: soc/intel/alderlake: Fix PCI IRQ tables

[Furquan Shaikh (Code Review)]

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph, Boris Mittelberg.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50599 )

Change subject: soc/intel/alderlake: Fix PCI IRQ tables
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Patch Set 4:

(2 comments)

File src/soc/intel/alderlake/acpi/pci_irqs.asl:

https://review.coreboot.org/c/coreboot/+/50599/comment/e3198edf_2835457b 
PS4, Line 6: Package(){0x001FFFFF, 0, 0, TRACEHUB_IRQ },
           : 	Package(){0x001FFFFF, 1, 0, HDA_IRQ },
           : 	Package(){0x001FFFFF, 2, 0, SMBUS_IRQ },
           : 	Package(){0x001FFFFF, 3, 0, GBE_IRQ },
I had dumped FSP logs last week and I see that for D31 all functions use INTA which is IRQ#16.

https://review.coreboot.org/c/coreboot/+/50599/comment/1d3df75d_0e292e9c 
PS4, Line 44: CNVI_WIFI_IRQ
D20F3 seems to be configured for INTA which is IRQ#16.