Change in coreboot[master]: security/intel/txt/romstage.c: Unlock memory when SCLEAN not needed - coreboot-gerrit

21 Nov 2021


      Attention is currently required from: Michał Żygowski.
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59521 )
Change subject: security/intel/txt/romstage.c: Unlock memory when SCLEAN not needed
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Patch Set 2: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59521/comment/f8fcad53_ad833c4e 
PS2, Line 10: memory on a TXT enabled platform. Previosuly on Sandybridge raminit the
this MSR is actually written in init_dram_ddr3(). Do you need to remove the code in src/northbridge/intel/sandybridge/raminit.c at some point?
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Idd29d163a2310f0b574fc72d575f23088ab1d11d
Gerrit-Change-Number: 59521
Gerrit-PatchSet: 2
Gerrit-Owner: Michał Żygowski michal.zygowski@3mdeb.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
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