Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45677 )
Change subject: soc/intel: Use ASL 2.0 syntax for GPIO ASL helper function ......................................................................
soc/intel: Use ASL 2.0 syntax for GPIO ASL helper function
Migrate ASL helper function like GRXS, GTXS, STXS, CTXS to ASL 2.0 syntax across CNL, ICL, JSL, SKL.
Change-Id: I0ebf1f86031eae25337d2dbeabb8893d9f19a14b Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/cannonlake/acpi/gpio_op.asl M src/soc/intel/icelake/acpi/gpio.asl M src/soc/intel/jasperlake/acpi/gpio_op.asl M src/soc/intel/skylake/acpi/gpio.asl 4 files changed, 22 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/45677/1
diff --git a/src/soc/intel/cannonlake/acpi/gpio_op.asl b/src/soc/intel/cannonlake/acpi/gpio_op.asl index 3c0ed66..1eedc88 100644 --- a/src/soc/intel/cannonlake/acpi/gpio_op.asl +++ b/src/soc/intel/cannonlake/acpi/gpio_op.asl @@ -11,7 +11,7 @@ { VAL0, 32 } - And (GPIORXSTATE_MASK, ShiftRight (VAL0, GPIORXSTATE_SHIFT), Local0) + Local0 = GPIORXSTATE_MASK & (VAL0 >> GPIORXSTATE_SHIFT)
Return (Local0) } @@ -27,7 +27,7 @@ { VAL0, 32 } - And (GPIOTXSTATE_MASK, VAL0, Local0) + Local0 = GPIOTXSTATE_MASK & VAL0
Return (Local0) } @@ -43,7 +43,7 @@ { VAL0, 32 } - Or (GPIOTXSTATE_MASK, VAL0, VAL0) + VAL0 = GPIOTXSTATE_MASK | VAL0 }
/* @@ -57,7 +57,7 @@ { VAL0, 32 } - And (Not (GPIOTXSTATE_MASK), VAL0, VAL0) + VAL0 = ~GPIOTXSTATE_MASK & VAL0 }
/* @@ -76,10 +76,9 @@ { VAL0, 32 } - Store (VAL0, Local0) - And (Not (GPIOPADMODE_MASK), Local0, Local0) - And (ShiftLeft (Arg1, GPIOPADMODE_SHIFT, Arg1), GPIOPADMODE_MASK, Arg1) - Or (Local0, Arg1, VAL0) + Local0 = ~GPIOPADMODE_MASK & VAL0 + Arg1 = (Arg1 << GPIOPADMODE_SHIFT) & GPIOPADMODE_MASK + VAL0 = Local0 | Arg1 }
/* @@ -97,10 +96,10 @@ VAL0, 32 }
- If (LEqual (Arg1, 1)) { - And (Not (GPIOTXBUFDIS_MASK), VAL0, VAL0) - } ElseIf (LEqual (Arg1, 0)){ - Or (GPIOTXBUFDIS_MASK, VAL0, VAL0) + If (Arg1 == 1) { + VAL0 = ~GPIOTXBUFDIS_MASK & VAL0 + } ElseIf (Arg1 == 0){ + VAL0 = GPIOTXBUFDIS_MASK | VAL0 } }
@@ -119,9 +118,9 @@ VAL0, 32 }
- If (LEqual (Arg1, 1)) { - And (Not (GPIORXBUFDIS_MASK), VAL0, VAL0) - } ElseIf (LEqual (Arg1, 0)){ - Or (GPIORXBUFDIS_MASK, VAL0, VAL0) + If (Arg1 == 1) { + VAL0 = ~GPIORXBUFDIS_MASK & VAL0 + } ElseIf (Arg1 == 0){ + VAL0 = GPIORXBUFDIS_MASK | VAL0 } } diff --git a/src/soc/intel/icelake/acpi/gpio.asl b/src/soc/intel/icelake/acpi/gpio.asl index 43aa83c..f0a6fa0 100644 --- a/src/soc/intel/icelake/acpi/gpio.asl +++ b/src/soc/intel/icelake/acpi/gpio.asl @@ -114,7 +114,7 @@ { VAL0, 32 } - And (GPIORXSTATE_MASK, ShiftRight (VAL0, GPIORXSTATE_SHIFT), Local0) + Local0 = GPIORXSTATE_MASK & (VAL0 >> GPIORXSTATE_SHIFT)
Return (Local0) } diff --git a/src/soc/intel/jasperlake/acpi/gpio_op.asl b/src/soc/intel/jasperlake/acpi/gpio_op.asl index 683686f..f7332aa 100644 --- a/src/soc/intel/jasperlake/acpi/gpio_op.asl +++ b/src/soc/intel/jasperlake/acpi/gpio_op.asl @@ -76,9 +76,8 @@ { VAL0, 32 } - Local0 = VAL0 - Local0 = ~PAD_CFG0_MODE_MASK & Local0 - Arg1 = (Arg1 <<= PAD_CFG0_MODE_SHIFT) & PAD_CFG0_MODE_MASK + Local0 = ~PAD_CFG0_MODE_MASK & VAL0 + Arg1 = (Arg1 << PAD_CFG0_MODE_SHIFT) & PAD_CFG0_MODE_MASK VAL0 = Local0 | Arg1 }
diff --git a/src/soc/intel/skylake/acpi/gpio.asl b/src/soc/intel/skylake/acpi/gpio.asl index 60e1cf5..436d7e6 100644 --- a/src/soc/intel/skylake/acpi/gpio.asl +++ b/src/soc/intel/skylake/acpi/gpio.asl @@ -119,7 +119,7 @@ { VAL0, 32 } - And (GPIORXSTATE_MASK, ShiftRight (VAL0, PAD_CFG0_RX_STATE_BIT), Local0) + Local0 = GPIORXSTATE_MASK & (VAL0 >> PAD_CFG0_RX_STATE_BIT)
Return (Local0) } @@ -135,7 +135,7 @@ { VAL0, 32 } - And (GPIOTXSTATE_MASK, ShiftRight (VAL0, PAD_CFG0_TX_STATE_BIT), Local0) + Local0 = GPIOTXSTATE_MASK & VAL0
Return (Local0) } @@ -151,7 +151,7 @@ { VAL0, 32 } - Or (GPIOTXSTATE_MASK, VAL0, VAL0) + VAL0 = GPIOTXSTATE_MASK | VAL0 }
/* @@ -165,5 +165,5 @@ { VAL0, 32 } - And (Not (GPIOTXSTATE_MASK), VAL0, VAL0) + VAL0 = ~GPIOTXSTATE_MASK & VAL0 }
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45677 )
Change subject: soc/intel: Use ASL 2.0 syntax for GPIO ASL helper function ......................................................................
Patch Set 1: Code-Review+2
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45677 )
Change subject: soc/intel: Use ASL 2.0 syntax for GPIO ASL helper function ......................................................................
Patch Set 1:
(9 comments)
https://review.coreboot.org/c/coreboot/+/45677/1/src/soc/intel/skylake/acpi/... File src/soc/intel/skylake/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/45677/1/src/soc/intel/skylake/acpi/... PS1, Line 27: Store (^^PCRB (PID_GPIOCOM0), BAS0) : Store old syntax
https://review.coreboot.org/c/coreboot/+/45677/1/src/soc/intel/skylake/acpi/... PS1, Line 33: Store (^^PCRB (PID_GPIOCOM1), BAS1) : Store old
https://review.coreboot.org/c/coreboot/+/45677/1/src/soc/intel/skylake/acpi/... PS1, Line 39: Store (^^PCRB (PID_GPIOCOM3), BAS3) : Store old
https://review.coreboot.org/c/coreboot/+/45677/1/src/soc/intel/skylake/acpi/... PS1, Line 43: And ( old
https://review.coreboot.org/c/coreboot/+/45677/1/src/soc/intel/skylake/acpi/... PS1, Line 46: LEqual ( old
https://review.coreboot.org/c/coreboot/+/45677/1/src/soc/intel/skylake/acpi/... PS1, Line 47: Store (GPIO_IRQ14, IRQN) : } Else { : Store old
https://review.coreboot.org/c/coreboot/+/45677/1/src/soc/intel/skylake/acpi/... PS1, Line 69: And (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Ar old
https://review.coreboot.org/c/coreboot/+/45677/1/src/soc/intel/skylake/acpi/... PS1, Line 71: Store (PID_GPIOCOM0, Local0) : Subtract (Arg0, GPP_A0, Local1) : } : /* GPIO Community 1 */ : If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPP_H23))) : { : Store (PID_GPIOCOM1, Local0) : Subtract (Arg0, GPP_C0, Local1) : } : /* GPIO Community 03 */ : If (LAnd (LGreaterEqual (Arg0, GPP_I0), LLessEqual (Arg0, GPP_I10))) : { : Store (PID_GPIOCOM3, Local0) : Subtract (Arg0, GPP_I0, Local1) : } : #else : /* GPIO Community 0 */ : If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPP_B23))) : { : Store (PID_GPIOCOM0, Local0) : Subtract (Arg0, GPP_A0, Local1) : } : /* GPIO Community 1 */ : If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPP_E23))) : { : Store (PID_GPIOCOM1, Local0) : Subtract (Arg0, GPP_C0, Local1) : } : /* GPIO Community 03*/ : If (LAnd (LGreaterEqual (Arg0, GPP_F0), LLessEqual (Arg0, GPP_G7))) : { : Store (PID_GPIOCOM3, Local0) : Subtract (Arg0, old
https://review.coreboot.org/c/coreboot/+/45677/1/src/soc/intel/skylake/acpi/... PS1, Line 106: Store (PCRB (Local0), Local2) : Add ( old
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45677 )
Change subject: soc/intel: Use ASL 2.0 syntax for GPIO ASL helper function ......................................................................
Patch Set 1:
HI HAOUAS Elyes,
I'm "not" claiming that i have migrating entire gpio*.asl into ASL2.0 syntax. The only helper function i'm heading into common code in patch trend is only addressed in this CL (like those function as GRXS, GTXS etc.).
if you see https://review.coreboot.org/q/topic:%22intel-asl-2-0%22+(status:open%20OR%20...) we have migrate all latest ASL code into 2.0 syntax hence its extra work to support such older platform and honestly i'm not looking to do this in middle of ADL upstream work. Hope you understood and its okay with you. 😊
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45677 )
Change subject: soc/intel: Use ASL 2.0 syntax for GPIO ASL helper function ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/45677/1/src/soc/intel/cannonlake/ac... File src/soc/intel/cannonlake/acpi/gpio_op.asl:
https://review.coreboot.org/c/coreboot/+/45677/1/src/soc/intel/cannonlake/ac... PS1, Line 100: VAL0 = ~GPIOTXBUFDIS_MASK & VAL0 VAL0 &= ~GPIOTXBUFDIS_MASK
https://review.coreboot.org/c/coreboot/+/45677/1/src/soc/intel/cannonlake/ac... PS1, Line 102: VAL0 = GPIOTXBUFDIS_MASK | VAL0 VAL0 |= GPIOTXBUFDIS_MASK
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45677 )
Change subject: soc/intel: Use ASL 2.0 syntax for GPIO ASL helper function ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45677/1/src/soc/intel/icelake/acpi/... File src/soc/intel/icelake/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/45677/1/src/soc/intel/icelake/acpi/... PS1, Line 35: Store (^^PCRB (PID_GPIOCOM1), BAS1) : Store old
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45677 )
Change subject: soc/intel: Use ASL 2.0 syntax for GPIO ASL helper function ......................................................................
Patch Set 1:
(2 comments)
Except ASL2.0 entire file migration comment all other comments been addressed with this patchset
https://review.coreboot.org/c/coreboot/+/45677/1/src/soc/intel/cannonlake/ac... File src/soc/intel/cannonlake/acpi/gpio_op.asl:
https://review.coreboot.org/c/coreboot/+/45677/1/src/soc/intel/cannonlake/ac... PS1, Line 100: VAL0 = ~GPIOTXBUFDIS_MASK & VAL0
VAL0 &= ~GPIOTXBUFDIS_MASK
Ack
https://review.coreboot.org/c/coreboot/+/45677/1/src/soc/intel/cannonlake/ac... PS1, Line 102: VAL0 = GPIOTXBUFDIS_MASK | VAL0
VAL0 |= GPIOTXBUFDIS_MASK
Ack
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45677
to look at the new patch set (#2).
Change subject: soc/intel: Use ASL 2.0 syntax for GPIO ASL helper function ......................................................................
soc/intel: Use ASL 2.0 syntax for GPIO ASL helper function
Migrate ASL helper function like GRXS, GTXS, STXS, CTXS to ASL 2.0 syntax across CNL, ICL, JSL, SKL.
Change-Id: I0ebf1f86031eae25337d2dbeabb8893d9f19a14b Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/cannonlake/acpi/gpio_op.asl M src/soc/intel/icelake/acpi/gpio.asl M src/soc/intel/skylake/acpi/gpio.asl 3 files changed, 20 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/45677/2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45677 )
Change subject: soc/intel: Use ASL 2.0 syntax for GPIO ASL helper function ......................................................................
Patch Set 2:
(9 comments)
https://review.coreboot.org/c/coreboot/+/45677/1/src/soc/intel/skylake/acpi/... File src/soc/intel/skylake/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/45677/1/src/soc/intel/skylake/acpi/... PS1, Line 27: Store (^^PCRB (PID_GPIOCOM0), BAS0) : Store
old syntax
CB:45691
Was it necessary to open so many comments about it, though? One would have sufficed.
https://review.coreboot.org/c/coreboot/+/45677/1/src/soc/intel/skylake/acpi/... PS1, Line 33: Store (^^PCRB (PID_GPIOCOM1), BAS1) : Store
old
CB:45691
https://review.coreboot.org/c/coreboot/+/45677/1/src/soc/intel/skylake/acpi/... PS1, Line 39: Store (^^PCRB (PID_GPIOCOM3), BAS3) : Store
old
CB:45691
https://review.coreboot.org/c/coreboot/+/45677/1/src/soc/intel/skylake/acpi/... PS1, Line 43: And (
old
CB:45691
https://review.coreboot.org/c/coreboot/+/45677/1/src/soc/intel/skylake/acpi/... PS1, Line 46: LEqual (
old
CB:45691
https://review.coreboot.org/c/coreboot/+/45677/1/src/soc/intel/skylake/acpi/... PS1, Line 47: Store (GPIO_IRQ14, IRQN) : } Else { : Store
old
CB:45691
https://review.coreboot.org/c/coreboot/+/45677/1/src/soc/intel/skylake/acpi/... PS1, Line 69: And (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Ar
old
CB:45691
https://review.coreboot.org/c/coreboot/+/45677/1/src/soc/intel/skylake/acpi/... PS1, Line 71: Store (PID_GPIOCOM0, Local0) : Subtract (Arg0, GPP_A0, Local1) : } : /* GPIO Community 1 */ : If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPP_H23))) : { : Store (PID_GPIOCOM1, Local0) : Subtract (Arg0, GPP_C0, Local1) : } : /* GPIO Community 03 */ : If (LAnd (LGreaterEqual (Arg0, GPP_I0), LLessEqual (Arg0, GPP_I10))) : { : Store (PID_GPIOCOM3, Local0) : Subtract (Arg0, GPP_I0, Local1) : } : #else : /* GPIO Community 0 */ : If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPP_B23))) : { : Store (PID_GPIOCOM0, Local0) : Subtract (Arg0, GPP_A0, Local1) : } : /* GPIO Community 1 */ : If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPP_E23))) : { : Store (PID_GPIOCOM1, Local0) : Subtract (Arg0, GPP_C0, Local1) : } : /* GPIO Community 03*/ : If (LAnd (LGreaterEqual (Arg0, GPP_F0), LLessEqual (Arg0, GPP_G7))) : { : Store (PID_GPIOCOM3, Local0) : Subtract (Arg0,
old
CB:45691
https://review.coreboot.org/c/coreboot/+/45677/1/src/soc/intel/skylake/acpi/... PS1, Line 106: Store (PCRB (Local0), Local2) : Add (
old
CB:45691
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45677 )
Change subject: soc/intel: Use ASL 2.0 syntax for GPIO ASL helper function ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45677/1/src/soc/intel/icelake/acpi/... File src/soc/intel/icelake/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/45677/1/src/soc/intel/icelake/acpi/... PS1, Line 35: Store (^^PCRB (PID_GPIOCOM1), BAS1) : Store
old
CB:45692
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45677 )
Change subject: soc/intel: Use ASL 2.0 syntax for GPIO ASL helper function ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45677/2/src/soc/intel/skylake/acpi/... File src/soc/intel/skylake/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/45677/2/src/soc/intel/skylake/acpi/... PS2, Line 138: And (GPIOTXSTATE_MASK, ShiftRight (VAL0, PAD_CFG0_TX_STATE_BIT), Local0) sorry, I don't understand how you got "Local0 = GPIOTXSTATE_MASK & VAL0"
shouldn't be Local0 = GPIOTXSTATE_MASK & (VAL0 >> PAD_CFG0_TX_STATE_BIT) ?
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45677 )
Change subject: soc/intel: Use ASL 2.0 syntax for GPIO ASL helper function ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45677/2/src/soc/intel/skylake/acpi/... File src/soc/intel/skylake/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/45677/2/src/soc/intel/skylake/acpi/... PS2, Line 138: And (GPIOTXSTATE_MASK, ShiftRight (VAL0, PAD_CFG0_TX_STATE_BIT), Local0)
sorry, I don't understand how you got "Local0 = GPIOTXSTATE_MASK & VAL0" […]
#define PAD_CFG0_TX_STATE_BIT 0 hence ignored
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45677 )
Change subject: soc/intel: Use ASL 2.0 syntax for GPIO ASL helper function ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45677/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45677/3//COMMIT_MSG@11 PS3, Line 11: Try abuild timeless to ensure there are no functional changes?
Subrata Banik has uploaded a new patch set (#4) to the change originally created by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/45677 )
Change subject: soc/intel: Use ASL 2.0 syntax for GPIO ASL helper function ......................................................................
soc/intel: Use ASL 2.0 syntax for GPIO ASL helper function
Migrate ASL helper function like GRXS, GTXS, STXS, CTXS to ASL 2.0 syntax across CNL, ICL, JSL, SKL.
TEST=Able to build and boot Hatch, EVE and ICLRVP platform. Dump and disassemble DSDT to ensure GRXS,GTXS etc functions implementation remain unchanged prior and after this CL.
Change-Id: I0ebf1f86031eae25337d2dbeabb8893d9f19a14b Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/cannonlake/acpi/gpio_op.asl M src/soc/intel/icelake/acpi/gpio.asl M src/soc/intel/skylake/acpi/gpio.asl 3 files changed, 20 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/45677/4
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45677 )
Change subject: soc/intel: Use ASL 2.0 syntax for GPIO ASL helper function ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45677/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45677/3//COMMIT_MSG@11 PS3, Line 11:
Try abuild timeless to ensure there are no functional changes?
Yes Furquan, I did so.
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45677 )
Change subject: soc/intel: Use ASL 2.0 syntax for GPIO ASL helper function ......................................................................
Patch Set 4: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45677 )
Change subject: soc/intel: Use ASL 2.0 syntax for GPIO ASL helper function ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45677/2/src/soc/intel/skylake/acpi/... File src/soc/intel/skylake/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/45677/2/src/soc/intel/skylake/acpi/... PS2, Line 138: And (GPIOTXSTATE_MASK, ShiftRight (VAL0, PAD_CFG0_TX_STATE_BIT), Local0)
#define PAD_CFG0_TX_STATE_BIT 0 hence ignored
This should be taken care of at the end of the patch train, when only one copy of this method remains.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45677 )
Change subject: soc/intel: Use ASL 2.0 syntax for GPIO ASL helper function ......................................................................
Patch Set 4: Code-Review+2
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45677 )
Change subject: soc/intel: Use ASL 2.0 syntax for GPIO ASL helper function ......................................................................
Patch Set 4: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/45677/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45677/3//COMMIT_MSG@11 PS3, Line 11:
Yes Furquan, I did so.
FYI, with ASL changes, I don't think you need to do a timeless build, you can just do a before/after diff of the fallback/dsdt.aml file, which I don't believe has any versioning or timestamps
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45677 )
Change subject: soc/intel: Use ASL 2.0 syntax for GPIO ASL helper function ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45677/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45677/3//COMMIT_MSG@11 PS3, Line 11:
FYI, with ASL changes, I don't think you need to do a timeless build, you can just do a before/after […]
That would work too, but abuild --timeless is easier to automate for bulk testing several platforms.
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45677 )
Change subject: soc/intel: Use ASL 2.0 syntax for GPIO ASL helper function ......................................................................
soc/intel: Use ASL 2.0 syntax for GPIO ASL helper function
Migrate ASL helper function like GRXS, GTXS, STXS, CTXS to ASL 2.0 syntax across CNL, ICL, JSL, SKL.
TEST=Able to build and boot Hatch, EVE and ICLRVP platform. Dump and disassemble DSDT to ensure GRXS,GTXS etc functions implementation remain unchanged prior and after this CL.
Change-Id: I0ebf1f86031eae25337d2dbeabb8893d9f19a14b Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/45677 Reviewed-by: HAOUAS Elyes ehaouas@noos.fr Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/cannonlake/acpi/gpio_op.asl M src/soc/intel/icelake/acpi/gpio.asl M src/soc/intel/skylake/acpi/gpio.asl 3 files changed, 20 insertions(+), 21 deletions(-)
Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, approved Angel Pons: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/soc/intel/cannonlake/acpi/gpio_op.asl b/src/soc/intel/cannonlake/acpi/gpio_op.asl index 3c0ed66..7f2a40c 100644 --- a/src/soc/intel/cannonlake/acpi/gpio_op.asl +++ b/src/soc/intel/cannonlake/acpi/gpio_op.asl @@ -11,7 +11,7 @@ { VAL0, 32 } - And (GPIORXSTATE_MASK, ShiftRight (VAL0, GPIORXSTATE_SHIFT), Local0) + Local0 = GPIORXSTATE_MASK & (VAL0 >> GPIORXSTATE_SHIFT)
Return (Local0) } @@ -27,7 +27,7 @@ { VAL0, 32 } - And (GPIOTXSTATE_MASK, VAL0, Local0) + Local0 = GPIOTXSTATE_MASK & VAL0
Return (Local0) } @@ -43,7 +43,7 @@ { VAL0, 32 } - Or (GPIOTXSTATE_MASK, VAL0, VAL0) + VAL0 |= GPIOTXSTATE_MASK }
/* @@ -57,7 +57,7 @@ { VAL0, 32 } - And (Not (GPIOTXSTATE_MASK), VAL0, VAL0) + VAL0 &= ~GPIOTXSTATE_MASK }
/* @@ -76,10 +76,9 @@ { VAL0, 32 } - Store (VAL0, Local0) - And (Not (GPIOPADMODE_MASK), Local0, Local0) - And (ShiftLeft (Arg1, GPIOPADMODE_SHIFT, Arg1), GPIOPADMODE_MASK, Arg1) - Or (Local0, Arg1, VAL0) + Local0 = ~GPIOPADMODE_MASK & VAL0 + Arg1 = (Arg1 << GPIOPADMODE_SHIFT) & GPIOPADMODE_MASK + VAL0 = Local0 | Arg1 }
/* @@ -97,10 +96,10 @@ VAL0, 32 }
- If (LEqual (Arg1, 1)) { - And (Not (GPIOTXBUFDIS_MASK), VAL0, VAL0) - } ElseIf (LEqual (Arg1, 0)){ - Or (GPIOTXBUFDIS_MASK, VAL0, VAL0) + If (Arg1 == 1) { + VAL0 &= ~GPIOTXBUFDIS_MASK + } ElseIf (Arg1 == 0){ + VAL0 |= GPIOTXBUFDIS_MASK } }
@@ -119,9 +118,9 @@ VAL0, 32 }
- If (LEqual (Arg1, 1)) { - And (Not (GPIORXBUFDIS_MASK), VAL0, VAL0) - } ElseIf (LEqual (Arg1, 0)){ - Or (GPIORXBUFDIS_MASK, VAL0, VAL0) + If (Arg1 == 1) { + VAL0 &= ~GPIORXBUFDIS_MASK + } ElseIf (Arg1 == 0){ + VAL0 |= GPIORXBUFDIS_MASK } } diff --git a/src/soc/intel/icelake/acpi/gpio.asl b/src/soc/intel/icelake/acpi/gpio.asl index 43aa83c..f0a6fa0 100644 --- a/src/soc/intel/icelake/acpi/gpio.asl +++ b/src/soc/intel/icelake/acpi/gpio.asl @@ -114,7 +114,7 @@ { VAL0, 32 } - And (GPIORXSTATE_MASK, ShiftRight (VAL0, GPIORXSTATE_SHIFT), Local0) + Local0 = GPIORXSTATE_MASK & (VAL0 >> GPIORXSTATE_SHIFT)
Return (Local0) } diff --git a/src/soc/intel/skylake/acpi/gpio.asl b/src/soc/intel/skylake/acpi/gpio.asl index 60e1cf5..de6ff42 100644 --- a/src/soc/intel/skylake/acpi/gpio.asl +++ b/src/soc/intel/skylake/acpi/gpio.asl @@ -119,7 +119,7 @@ { VAL0, 32 } - And (GPIORXSTATE_MASK, ShiftRight (VAL0, PAD_CFG0_RX_STATE_BIT), Local0) + Local0 = GPIORXSTATE_MASK & (VAL0 >> PAD_CFG0_RX_STATE_BIT)
Return (Local0) } @@ -135,7 +135,7 @@ { VAL0, 32 } - And (GPIOTXSTATE_MASK, ShiftRight (VAL0, PAD_CFG0_TX_STATE_BIT), Local0) + Local0 = GPIOTXSTATE_MASK & VAL0
Return (Local0) } @@ -151,7 +151,7 @@ { VAL0, 32 } - Or (GPIOTXSTATE_MASK, VAL0, VAL0) + VAL0 |= GPIOTXSTATE_MASK }
/* @@ -165,5 +165,5 @@ { VAL0, 32 } - And (Not (GPIOTXSTATE_MASK), VAL0, VAL0) + VAL0 &= ~GPIOTXSTATE_MASK }