Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38978 )
Change subject: [WIP] mb/acer: Add Acer Aspire ES1-572 ......................................................................
Patch Set 6:
(18 comments)
This change is ready for review.
https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG@12 PS5, Line 12: Tested and working:
that's the USB on M. […]
Ack. Will test again alongside Wi-Fi.
https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG@19 PS5, Line 19: - Loading Linux with SeaBIOS and tianocore
booting linux with grub2 works fine, too
Ack
https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG@20 PS5, Line 20: - Power button soldered onto the board's debug pads.
-> maybe add that to Documentation/mb/...
Ack
https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG@21 PS5, Line 21: - UART 2 to get yelled at
-> maybe add info on how to access that + resistor names to Documentation/mb/...
Ack
https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG@24 PS5, Line 24: Not working or need testing:
Might be due to something weird w.r.t. […]
I had problems at some point. No idea why.
https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG@25 PS5, Line 25: - Wi-Fi card. Probably fixed with correct PCIe settings.
working perfectly with iwlwifi and firmware-iwlwifi installed on debian
Ack. I had problems so I'll re-test it when I find the M.2 card.
https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG@29 PS5, Line 29: - Internal eDP LCD. I think I have the cable somewhere.
... […]
Ack
https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG@30 PS5, Line 30: - Lid. It was brutally damaged, even though the LCD managed to survive.
nope, it's connected to the EC
Ack
https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG@31 PS5, Line 31: - Battery. I have it somewhere.
oh nice! unfortunately I have zero knowlege of ACPI \o/ I will check that as soon as I have some tim […]
I'm cleaning up comments on older patchsets. I still have a [WIP] in the commit message because EC support is null
https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG@32 PS5, Line 32: Keyboard
I had grub running and typed some text and numbers; arrows are fine; dunno: windows key, context me […]
Ack
https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG@33 PS5, Line 33: .
I placed them for consistency with other entries with multiple sentences.
Ack
https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG@33 PS5, Line 33: Card reader
works fine
Ack
https://review.coreboot.org/c/coreboot/+/38978/5/acer_a_thing.defconfig File acer_a_thing.defconfig:
https://review.coreboot.org/c/coreboot/+/38978/5/acer_a_thing.defconfig@2 PS5, Line 2: CONFIG_VENDOR_ACER=y
Oh, I'm still carrying this over? I don't need it anymore
Gone.
https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572/... File src/mainboard/acer/es1-572/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572/... PS5, Line 16: ramstage-y += ramstage.c
The filename would then be less descriptive. Also, see CB:41106.
Did not
https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572/... PS5, Line 17: ramstage-y += hda_verb.c
Only when CONFIG_AZALIA_PLUGIN_SUPPORT=y. […]
HDA has no verbs yet
https://review.coreboot.org/c/coreboot/+/38978/4/src/mainboard/acer/es1-572/... File src/mainboard/acer/es1-572/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38978/4/src/mainboard/acer/es1-572/... PS4, Line 129: #| AC LoadLine | 15 mOhm | 5.7 mOhm | 5.2 mOhm | 5.2 mOhm |
Since we can assume that the NCP81208 supports PS3/4 the whole vr_config can be dropped as soon as c […]
Gone.
https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572/... File src/mainboard/acer/es1-572/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572/... PS5, Line 113: PchSerialIoPci
I'll try to use SkipInit and hope it works. […]
SkipInit works.
https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572/... PS5, Line 266: device pci 1f.5 off end # PCH SPI
Off-topic, but presently, lpc_set_lock_enable in the common code locks BIOS write-enable=1. […]
Ack
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Angel Pons (Code Review)