Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35403 )
Change subject: soc/intel/common/basecode: Implement CSE update flow
......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35403/1/src/soc/intel/common/baseco...
File src/soc/intel/common/basecode/fw_update/cse_update.c:
https://review.coreboot.org/c/coreboot/+/35403/1/src/soc/intel/common/baseco...
PS1, Line 129: /* Create a RW partition region device to work with */
: rw_region.offset = part_info.bp_entries[RW_BP2].bp_start_offset
: + region_device_offset(&me_region);
: rw_region.size = (part_info.bp_entries[RW_BP3].bp_end_offset
: - part_info.bp_entries[RW_BP2].bp_start_offset) + 1;
: printk(BIOS_DEBUG, "Update ME_RW region: offset = 0x%x, size = 0x%x\n",
: (uint32_t)rw_region.offset, (uint32_t)rw_region.size);
CSE region will be divided into 2 partitions (RO & RW). […]
Done
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Gerrit-Project: coreboot
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