yuchi.chen@intel.com has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83315?usp=email )
Change subject: src/soc/intel/common/block/include/intelblocks/gpio.h: add pad_own_reg_0 field ......................................................................
src/soc/intel/common/block/include/intelblocks/gpio.h: add pad_own_reg_0 field
Change-Id: I30a934fd00a7a42cb156341da1954e4e4b1231d8 Signed-off-by: Yuchi Chen yuchi.chen@intel.com --- M src/soc/intel/common/block/include/intelblocks/gpio.h 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/83315/1
diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h index a7bb332..2c47d68 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio.h @@ -121,6 +121,7 @@ Number of pads bit mapped in each GPI status/en and Host Own Reg */ gpio_t first_pad; /* first pad in community */ gpio_t last_pad; /* last pad in community */ + uint16_t pad_own_reg_0; /* offset to Pad Ownership Reg 0 */ uint16_t host_own_reg_0; /* offset to Host Ownership Reg 0 */ uint16_t gpi_int_sts_reg_0; /* offset to GPI Int STS Reg 0 */ uint16_t gpi_int_en_reg_0; /* offset to GPI Int Enable Reg 0 */