Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83948?usp=email )
Change subject: soc/intel/common/block/cpu: Fix number of way computation regression ......................................................................
soc/intel/common/block/cpu: Fix number of way computation regression
Commit a549b09de4ffa30989d42ad2939630e9f854d6d9 ("soc/intel/common: Calculate and configure SF Mask 2") breaks the computation of the number of way and as result, all the derived masks. It results in MSR such as `IA32_L3_MASK_1' to be improperly programmed yielding unpredictable NEM issues such as hangs.
Indeed, this commit has introduced a backup of 0x1 into %edx before comparing the requested cache-as-RAM size against the way size. When the requested cache-as-RAM is larger, it reaches the second part of the algorithm which computes the necessary number of way to fit the requested cache-as-RAM.
This algorithm uses the `div' instruction. Per specification, the div instruction divides the 64 bits combination of %edx and %eax register. Since 0x1 got backed up in %edx and assuming a `CONFIG_DCACHE_RAM_SIZE' of 0x200000, we end up dividing 0x100200000 by the way size instead of 0x200000 which result in a necessary number of ways of 4098 for a way size of 0x100000. The mask computation using only the lower bit of %ecx (%cl), it adds some extra "randomness".
This commit clears the %edx register before calling the `div' instruction.
BUG=b:TBD TEST=Verified on rex
Change-Id: I5cb66da0aa977eecb64a0021268a6827747c521d Signed-off-by: Jeremy Compostella jeremy.compostella@intel.com --- M src/soc/intel/common/block/cpu/car/cache_as_ram.S 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/83948/1
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index f68ac4c..05e7a35 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -523,6 +523,7 @@ * ways to be configured for non-eviction */ mov $CONFIG_DCACHE_RAM_SIZE, %eax + xor %edx, %edx div %ecx mov %eax, %edx /* back up data_ways in edx */ mov %eax, %ecx