mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35494 )
Change subject: sc7180: initial SoC support ......................................................................
sc7180: initial SoC support
Change-Id: Iddcef560c1987486436b73ca1d5fc83cee2f713c Signed-off-by: T Michael Turney mturney@codeaurora.org --- A src/soc/qualcomm/sc7180/Kconfig A src/soc/qualcomm/sc7180/Makefile.inc A src/soc/qualcomm/sc7180/bootblock.c A src/soc/qualcomm/sc7180/cbmem.c A src/soc/qualcomm/sc7180/gpio.c A src/soc/qualcomm/sc7180/include/soc/addressmap.h A src/soc/qualcomm/sc7180/include/soc/gpio.h A src/soc/qualcomm/sc7180/include/soc/memlayout.ld A src/soc/qualcomm/sc7180/include/soc/mmu.h A src/soc/qualcomm/sc7180/include/soc/symbols.h A src/soc/qualcomm/sc7180/mmu.c A src/soc/qualcomm/sc7180/qclib.c A src/soc/qualcomm/sc7180/soc.c A src/soc/qualcomm/sc7180/spi.c A src/soc/qualcomm/sc7180/timer.c A src/soc/qualcomm/sc7180/uart_bitbang.c 16 files changed, 642 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/35494/1
diff --git a/src/soc/qualcomm/sc7180/Kconfig b/src/soc/qualcomm/sc7180/Kconfig new file mode 100644 index 0000000..70737e9 --- /dev/null +++ b/src/soc/qualcomm/sc7180/Kconfig @@ -0,0 +1,25 @@ + +config SOC_QUALCOMM_SC7180 + bool + default n + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select GENERIC_GPIO_LIB + select GENERIC_UDELAY + select HAVE_MONOTONIC_TIMER + select ARM64_USE_ARCH_TIMER + select SOC_QUALCOMM_COMMON + select HAVE_UART_SPECIAL + select BOOTBLOCK_CONSOLE + +if SOC_QUALCOMM_SC7180 + +config VBOOT + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_RETURN_FROM_VERSTAGE + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_BOOTBLOCK + +endif diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc new file mode 100644 index 0000000..a973724 --- /dev/null +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -0,0 +1,47 @@ + +ifeq ($(CONFIG_SOC_QUALCOMM_SC7180),y) + +################################################################################ +bootblock-y += bootblock.c +bootblock-y += mmu.c +bootblock-y += timer.c +bootblock-y += gpio.c +bootblock-y += spi.c +bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c + +################################################################################ +verstage-y += timer.c +verstage-y += gpio.c +verstage-y += spi.c +verstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c + +################################################################################ +romstage-y += cbmem.c +romstage-y += timer.c +romstage-y += gpio.c +romstage-y += ../common/qclib.c +romstage-y += ../common/mmu.c +romstage-y += mmu.c +romstage-y += spi.c +romstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c + +################################################################################ +ramstage-y += soc.c +ramstage-y += cbmem.c +ramstage-y += timer.c +ramstage-y += gpio.c +ramstage-y += spi.c +ramstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c + +################################################################################ + +CPPFLAGS_common += -Isrc/soc/qualcomm/sc7180/include +CPPFLAGS_common += -Isrc/soc/qualcomm/common/include + +################################################################################ + +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin + @printf "Generating: $(subst $(obj)/,,$(@))\n" + cp $(objcbfs)/bootblock.raw.bin $(objcbfs)/bootblock.bin + +endif diff --git a/src/soc/qualcomm/sc7180/bootblock.c b/src/soc/qualcomm/sc7180/bootblock.c new file mode 100644 index 0000000..b9b8660 --- /dev/null +++ b/src/soc/qualcomm/sc7180/bootblock.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <soc/mmu.h> + +void bootblock_soc_init(void) +{ + sc7180_mmu_init(); +} diff --git a/src/soc/qualcomm/sc7180/cbmem.c b/src/soc/qualcomm/sc7180/cbmem.c new file mode 100644 index 0000000..597e369 --- /dev/null +++ b/src/soc/qualcomm/sc7180/cbmem.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> + +void *cbmem_top(void) +{ + return (void *)((uintptr_t)4 * GiB); +} diff --git a/src/soc/qualcomm/sc7180/gpio.c b/src/soc/qualcomm/sc7180/gpio.c new file mode 100644 index 0000000..bb5baf5 --- /dev/null +++ b/src/soc/qualcomm/sc7180/gpio.c @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018-2019 Qualcomm Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/mmio.h> +#include <assert.h> +#include <types.h> +#include <gpio.h> + +void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, + uint32_t drive_str, uint32_t enable) +{ + +} + +void gpio_set(gpio_t gpio, int value) +{ + +} + +int gpio_get(gpio_t gpio) +{ + return 0; +} + +void gpio_input_pulldown(gpio_t gpio) +{ + +} + +void gpio_input_pullup(gpio_t gpio) +{ + +} + +void gpio_input(gpio_t gpio) +{ + +} + +void gpio_output(gpio_t gpio, int value) +{ + +} + +void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull) +{ + +} + +int gpio_irq_status(gpio_t gpio) +{ + return 0; +} diff --git a/src/soc/qualcomm/sc7180/include/soc/addressmap.h b/src/soc/qualcomm/sc7180/include/soc/addressmap.h new file mode 100644 index 0000000..93f0481 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/addressmap.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2018-2019 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_SC7180_ADDRESS_MAP_H_ +#define _SOC_QUALCOMM_SC7180_ADDRESS_MAP_H_ + +#include <stdint.h> + +#endif /* _SOC_QUALCOMM_SC7180_ADDRESS_MAP_H_ */ diff --git a/src/soc/qualcomm/sc7180/include/soc/gpio.h b/src/soc/qualcomm/sc7180/include/soc/gpio.h new file mode 100644 index 0000000..170854c --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/gpio.h @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_SC7180_GPIO_H_ +#define _SOC_QUALCOMM_SC7180_GPIO_H_ + +#include <types.h> +#include <soc/addressmap.h> + +typedef struct { + u32 addr; +} gpio_t; + +/* GPIO TLMM: Direction */ +#define GPIO_INPUT 0 +#define GPIO_OUTPUT 1 + +/* GPIO TLMM: Pullup/Pulldown */ +#define GPIO_NO_PULL 0 +#define GPIO_PULL_DOWN 1 +#define GPIO_KEEPER 2 +#define GPIO_PULL_UP 3 + +/* GPIO TLMM: Status */ +#define GPIO_OUTPUT_DISABLE 0 +#define GPIO_OUTPUT_ENABLE 1 + +#define GPIO_FUNC_GPIO 0 + +#define GPIO(num) ((gpio_t){.addr = GPIO##num##_ADDR}) + +/* TODO: fill this in for Rennell */ +#if 0 +#define PIN(index, tlmm, func1, func2, func3, func4, func5, func6, func7) \ +GPIO##index##_ADDR = TLMM_##tlmm##_TILE_BASE + index * TLMM_GPIO_OFF_DELTA, \ +GPIO##index##_FUNC_##func1 = 1, \ +GPIO##index##_FUNC_##func2 = 2, \ +GPIO##index##_FUNC_##func3 = 3, \ +GPIO##index##_FUNC_##func4 = 4, \ +GPIO##index##_FUNC_##func5 = 5, \ +GPIO##index##_FUNC_##func6 = 6, \ +GPIO##index##_FUNC_##func7 = 7 + +enum { + PIN(0, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), +}; +#endif + +enum gpio_irq_type { + IRQ_TYPE_LEVEL = 0, + IRQ_TYPE_RISING_EDGE = 1, + IRQ_TYPE_FALLING_EDGE = 2, + IRQ_TYPE_DUAL_EDGE = 3, +}; + +struct tlmm_gpio { + uint32_t cfg; + uint32_t in_out; + uint32_t intr_cfg; + uint32_t intr_status; +}; + +void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, + uint32_t drive_str, uint32_t enable); +void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull); +int gpio_irq_status(gpio_t gpio); + +#endif /* _SOC_QUALCOMM_SC7180_GPIO_H_ */ diff --git a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld new file mode 100644 index 0000000..ae00816 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <memlayout.h> +#include <arch/header.ld> + +/* SYSTEM_IMEM : 0x14680000 - 0x14699000 */ +#define SSRAM_START(addr) SYMBOL(ssram, addr) +#define SSRAM_END(addr) SYMBOL(essram, addr) + +/* BOOT_IMEM : 0x14800000 - 0x14900000 */ +#define BSRAM_START(addr) SYMBOL(bsram, addr) +#define BSRAM_END(addr) SYMBOL(ebsram, addr) + +SECTIONS +{ + SSRAM_START(0x14680000) + OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 100K) + REGION(qcsdi, 0x14699000, 52K, 4K) + SSRAM_END(0x146A6000) + + BSRAM_START(0x14800000) + REGION(bsram_reserved1, 0x14800000, 84K, 4K) + BOOTBLOCK(0x14815000, 40K) + PRERAM_CBFS_CACHE(0x1481F000, 70K) + PRERAM_CBMEM_CONSOLE(0x14830800, 32K) + TIMESTAMP(0x14838800, 1K) + REGION(bsram_align1, 0x14838C00, 1K, 1K) + TTB(0x14839000, 56K) + STACK(0x14847000, 16K) + VBOOT2_WORK(0x1484B000, 12K) + DMA_COHERENT(0x1484E000, 8K) + REGION(ddr_training, 0x14850000, 8K, 4K) + REGION(qclib_serial_log, 0x14852000, 4K, 4K) + REGION(ddr_information, 0x14853000, 1K, 1K) + REGION(bsram_unused, 0x14853400, 0x1CC00, 1K) + REGION(dcb, 0x14870000, 16K, 4K) + REGION(pmic, 0x14874000, 44K, 4K) + REGION(limits_cfg, 0x1487F000, 4K, 4K) + REGION(qclib, 0x14880000, 512K, 4K) + BSRAM_END(0x14900000) + + DRAM_START(0x80000000) + REGION(dram_reserved1, 0x80820000, 0x20000, 0x1000) + REGION(dram_reserved, 0x80900000, 0x200000, 0x1000) + /* Various hardware/software subsystems make use of this area */ + BL31(0x85000000, 0x1A800000) + POSTRAM_CBFS_CACHE(0x9F800000, 384K) + RAMSTAGE(0x9F860000, 2M) +} diff --git a/src/soc/qualcomm/sc7180/include/soc/mmu.h b/src/soc/qualcomm/sc7180/include/soc/mmu.h new file mode 100644 index 0000000..735ce17 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/mmu.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_SC7180_MMU_H_ +#define _SOC_QUALCOMM_SC7180_MMU_H_ + +void sc7180_mmu_init(void); + +#endif /* _SOC_QUALCOMM_SC7180_MMU_H_ */ diff --git a/src/soc/qualcomm/sc7180/include/soc/symbols.h b/src/soc/qualcomm/sc7180/include/soc/symbols.h new file mode 100644 index 0000000..14b779f --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/symbols.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_SC7180_SYMBOLS_H_ +#define _SOC_QUALCOMM_SC7180_SYMBOLS_H_ + +#include <symbols.h> + +DECLARE_REGION(ssram) +DECLARE_REGION(bsram) +DECLARE_REGION(dram_reserved) +DECLARE_REGION(dram_reserved1) +DECLARE_REGION(el3_stack_canary); +DECLARE_REGION(dcb); +DECLARE_REGION(pmic); +DECLARE_REGION(limits_cfg); + +#endif /* _SOC_QUALCOMM_SC7180_SYMBOLS_H_ */ diff --git a/src/soc/qualcomm/sc7180/mmu.c b/src/soc/qualcomm/sc7180/mmu.c new file mode 100644 index 0000000..fd59a5a --- /dev/null +++ b/src/soc/qualcomm/sc7180/mmu.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <symbols.h> +#include <arch/mmu.h> +#include <arch/cache.h> +#include <soc/mmu.h> +#include <soc/mmu_common.h> +#include <soc/symbols.h> + +void sc7180_mmu_init(void) +{ + mmu_init(); + + mmu_config_range((void *)(4 * KiB), ((4UL * GiB) - (4 * KiB)), DEV_MEM); + mmu_config_range((void *)_ssram, REGION_SIZE(ssram), CACHED_RAM); + mmu_config_range((void *)_bsram, REGION_SIZE(bsram), CACHED_RAM); + mmu_config_range((void *)_dma_coherent, REGION_SIZE(dma_coherent), + UNCACHED_RAM); + + mmu_enable(); +} + diff --git a/src/soc/qualcomm/sc7180/qclib.c b/src/soc/qualcomm/sc7180/qclib.c new file mode 100644 index 0000000..9c05452 --- /dev/null +++ b/src/soc/qualcomm/sc7180/qclib.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <fmap.h> +#include <console/console.h> +#include <soc/symbols.h> +#include <soc/qclib_common.h> + +int qclib_soc_blob_load(void) +{ + size_t size; + ssize_t ssize; + + /* Attempt to load PMICCFG Blob */ + size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/pmiccfg", + _pmic, REGION_SIZE(pmic), CBFS_TYPE_RAW); + if (!size) + return -1; + qclib_add_if_table_entry(QCLIB_TE_PMIC_SETTINGS, _pmic, size, 0); + + /* Attempt to load DCB Blob */ + size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/dcb", + _dcb, REGION_SIZE(dcb), CBFS_TYPE_RAW); + if (!size) + return -1; + qclib_add_if_table_entry(QCLIB_TE_DCB_SETTINGS, _dcb, size, 0); + + /* Attempt to load Limits Config Blob */ + ssize = fmap_read_area(QCLIB_FR_LIMITS_CFG_DATA, _limits_cfg, + REGION_SIZE(limits_cfg)); + if (ssize < 0) + return -1; + qclib_add_if_table_entry(QCLIB_TE_LIMITS_CFG_DATA, + _limits_cfg, ssize, 0); + + return 0; +} diff --git a/src/soc/qualcomm/sc7180/soc.c b/src/soc/qualcomm/sc7180/soc.c new file mode 100644 index 0000000..4fc5b30 --- /dev/null +++ b/src/soc/qualcomm/sc7180/soc.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <symbols.h> +#include <device/device.h> +#include <soc/mmu.h> +#include <soc/mmu_common.h> +#include <soc/symbols.h> + +static void soc_read_resources(struct device *dev) +{ + ram_resource(dev, 0, (uintptr_t)ddr_region->offset / KiB, + ddr_region->size / KiB); + reserved_ram_resource(dev, 1, (uintptr_t)_dram_reserved / KiB, + REGION_SIZE(dram_reserved) / KiB); + reserved_ram_resource(dev, 2, (uintptr_t)_dram_reserved1 / KiB, + REGION_SIZE(dram_reserved1) / KiB); + + + +} + +static void soc_init(struct device *dev) +{ + +} + +static struct device_operations soc_ops = { + .read_resources = soc_read_resources, + .init = soc_init, +}; + +static void enable_soc_dev(struct device *dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_qualcomm_sc7180_ops = { + CHIP_NAME("SOC Qualcomm SC7180") + .enable_dev = enable_soc_dev, +}; diff --git a/src/soc/qualcomm/sc7180/spi.c b/src/soc/qualcomm/sc7180/spi.c new file mode 100644 index 0000000..5abb81a --- /dev/null +++ b/src/soc/qualcomm/sc7180/spi.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <spi-generic.h> +#include <spi_flash.h> + +static const struct spi_ctrlr spi_ctrlr; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_ctrlr, + .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + }, +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/soc/qualcomm/sc7180/timer.c b/src/soc/qualcomm/sc7180/timer.c new file mode 100644 index 0000000..5b78c1d --- /dev/null +++ b/src/soc/qualcomm/sc7180/timer.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <delay.h> +#include <arch/lib_helpers.h> +#include <commonlib/helpers.h> + +void init_timer(void) +{ + raw_write_cntfrq_el0(19200*KHz); +} diff --git a/src/soc/qualcomm/sc7180/uart_bitbang.c b/src/soc/qualcomm/sc7180/uart_bitbang.c new file mode 100644 index 0000000..813be89 --- /dev/null +++ b/src/soc/qualcomm/sc7180/uart_bitbang.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * Copyright 2019 The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/uart.h> +#include <gpio.h> +#include <types.h> + +#if 0 +#define UART_TX_PIN GPIO(4) +#else +#include <boot/coreboot_tables.h> +gpio_t uart_gpio = { 0 }; +#define UART_TX_PIN uart_gpio + +void uart_fill_lb(void *data) +{ + +} +#endif + + +static void set_tx(int line_state) +{ + gpio_set(UART_TX_PIN, line_state); +} + +void uart_init(int idx) +{ + gpio_output(UART_TX_PIN, 1); +} + +void uart_tx_byte(int idx, unsigned char data) +{ + uart_bitbang_tx_byte(data, set_tx); +} + +void uart_tx_flush(int idx) +{ + /* unnecessary, PIO Tx means transaction is over when tx_byte returns */ +} + +unsigned char uart_rx_byte(int idx) +{ + return 0; /* not implemented */ +}
Hello Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35494
to look at the new patch set (#2).
Change subject: sc7180: initial SoC support ......................................................................
sc7180: initial SoC support
Change-Id: Iddcef560c1987486436b73ca1d5fc83cee2f713c Signed-off-by: T Michael Turney mturney@codeaurora.org --- A src/soc/qualcomm/sc7180/Kconfig A src/soc/qualcomm/sc7180/Makefile.inc A src/soc/qualcomm/sc7180/bootblock.c A src/soc/qualcomm/sc7180/cbmem.c A src/soc/qualcomm/sc7180/gpio.c A src/soc/qualcomm/sc7180/include/soc/addressmap.h A src/soc/qualcomm/sc7180/include/soc/gpio.h A src/soc/qualcomm/sc7180/include/soc/memlayout.ld A src/soc/qualcomm/sc7180/include/soc/mmu.h A src/soc/qualcomm/sc7180/include/soc/symbols.h A src/soc/qualcomm/sc7180/mmu.c A src/soc/qualcomm/sc7180/qclib.c A src/soc/qualcomm/sc7180/soc.c A src/soc/qualcomm/sc7180/spi.c A src/soc/qualcomm/sc7180/timer.c A src/soc/qualcomm/sc7180/uart_bitbang.c 16 files changed, 622 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/35494/2
Hello Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35494
to look at the new patch set (#3).
Change subject: sc7180: initial SoC support ......................................................................
sc7180: initial SoC support
Change-Id: Iddcef560c1987486436b73ca1d5fc83cee2f713c Signed-off-by: T Michael Turney mturney@codeaurora.org --- A src/soc/qualcomm/sc7180/Kconfig A src/soc/qualcomm/sc7180/Makefile.inc A src/soc/qualcomm/sc7180/bootblock.c A src/soc/qualcomm/sc7180/cbmem.c A src/soc/qualcomm/sc7180/gpio.c A src/soc/qualcomm/sc7180/include/soc/addressmap.h A src/soc/qualcomm/sc7180/include/soc/gpio.h A src/soc/qualcomm/sc7180/include/soc/memlayout.ld A src/soc/qualcomm/sc7180/include/soc/mmu.h A src/soc/qualcomm/sc7180/include/soc/symbols.h A src/soc/qualcomm/sc7180/mmu.c A src/soc/qualcomm/sc7180/qclib.c A src/soc/qualcomm/sc7180/soc.c A src/soc/qualcomm/sc7180/spi.c A src/soc/qualcomm/sc7180/timer.c A src/soc/qualcomm/sc7180/uart_bitbang.c 16 files changed, 621 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/35494/3
Alexander Couzens has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35494 )
Change subject: sc7180: initial SoC support ......................................................................
Patch Set 4:
Hi Michael,
thanks for the support. Can you please add some documentation about the SoC to the docs/ directory? Also a brief description of the SoC to the commit message would be good. What's kind of arm core does it use? What peripherals does it have? [..]
Best Regards, lynxis
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35494 )
Change subject: sc7180: initial SoC support ......................................................................
Patch Set 5:
(12 comments)
https://review.coreboot.org/c/coreboot/+/35494/5/src/soc/qualcomm/sc7180/Mak... File src/soc/qualcomm/sc7180/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/35494/5/src/soc/qualcomm/sc7180/Mak... PS5, Line 43: $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin Don't need this as long as all we do is copying, there's already a generic rule for this in the toplevel Makefile.inc.
https://review.coreboot.org/c/coreboot/+/35494/5/src/soc/qualcomm/sc7180/gpi... File src/soc/qualcomm/sc7180/gpio.c:
https://review.coreboot.org/c/coreboot/+/35494/5/src/soc/qualcomm/sc7180/gpi... PS5, Line 1: /* Do we need to add this file now? Would prefer to leave it (and the bitbang UART depending on it) for a later patch where you actually add the implementation. (Just don't select GENERIC_GPIO_LIB for now.)
https://review.coreboot.org/c/coreboot/+/35494/5/src/soc/qualcomm/sc7180/inc... File src/soc/qualcomm/sc7180/include/soc/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/35494/5/src/soc/qualcomm/sc7180/inc... PS5, Line 19: 0x14699000 number doesn't match the one below?
https://review.coreboot.org/c/coreboot/+/35494/5/src/soc/qualcomm/sc7180/inc... PS5, Line 35: REGION(bsram_reserved1, 0x14800000, 84K, 4K) nit: Can we add a comment what it is reserved for? (I think I asked about this region on SDM845 already, don't remember if it was ever really answered...)
https://review.coreboot.org/c/coreboot/+/35494/5/src/soc/qualcomm/sc7180/inc... PS5, Line 40: REGION(bsram_align1, 0x14838C00, 1K, 1K) nit: No need to define regions for empty space, you can just leave it empty
https://review.coreboot.org/c/coreboot/+/35494/5/src/soc/qualcomm/sc7180/inc... PS5, Line 48: REGION(bsram_unused, 0x14853400, 0x1CC00, 1K) nit: same here
https://review.coreboot.org/c/coreboot/+/35494/5/src/soc/qualcomm/sc7180/inc... PS5, Line 57: REGION(dram_reserved, 0x80900000, 0x200000, 0x1000) nit: can we find better names to differentiate these two?
https://review.coreboot.org/c/coreboot/+/35494/5/src/soc/qualcomm/sc7180/inc... PS5, Line 58: /* Various hardware/software subsystems make use of this area */ This comment looks like it's supposed to be two lines earlier?
https://review.coreboot.org/c/coreboot/+/35494/5/src/soc/qualcomm/sc7180/inc... PS5, Line 61: RAMSTAGE(0x9F860000, 2M) nit: with the recent addition of FIT booting code (not used by Chrome OS (yet), but by others) which needs enough heap and CBFS scratch space to manipulate kernel and initramfs images, it has become en vogue to make these last two a lot bigger (e.g. 16MB each). Might as well do that if we have the space.
https://review.coreboot.org/c/coreboot/+/35494/5/src/soc/qualcomm/sc7180/inc... File src/soc/qualcomm/sc7180/include/soc/symbols.h:
https://review.coreboot.org/c/coreboot/+/35494/5/src/soc/qualcomm/sc7180/inc... PS5, Line 25: DECLARE_REGION(el3_stack_canary); Looks like this is a leftover that was already removed from SDM845 at some point?
https://review.coreboot.org/c/coreboot/+/35494/5/src/soc/qualcomm/sc7180/uar... File src/soc/qualcomm/sc7180/uart_bitbang.c:
https://review.coreboot.org/c/coreboot/+/35494/5/src/soc/qualcomm/sc7180/uar... PS5, Line 21: #if 0 Can't commit stuff like this. I'd just leave this file out until later when you can actually make it work. (Just don't select HAVE_UART_SPECIAL for now if it doesn't compile otherwise.)
https://review.coreboot.org/c/coreboot/+/35494/5/src/soc/qualcomm/sc7180/uar... PS5, Line 25: gpio_t uart_gpio = { 0 }; ...not really sure what this is all about, anyway?
mturney mturney has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35494 )
Change subject: sc7180: initial SoC support ......................................................................
Patch Set 6:
(12 comments)
https://review.coreboot.org/c/coreboot/+/35494/5/src/soc/qualcomm/sc7180/Mak... File src/soc/qualcomm/sc7180/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/35494/5/src/soc/qualcomm/sc7180/Mak... PS5, Line 43: $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
Don't need this as long as all we do is copying, there's already a generic rule for this in the topl […]
Done
https://review.coreboot.org/c/coreboot/+/35494/5/src/soc/qualcomm/sc7180/gpi... File src/soc/qualcomm/sc7180/gpio.c:
https://review.coreboot.org/c/coreboot/+/35494/5/src/soc/qualcomm/sc7180/gpi... PS5, Line 1: /*
Do we need to add this file now? Would prefer to leave it (and the bitbang UART depending on it) for […]
Done
https://review.coreboot.org/c/coreboot/+/35494/5/src/soc/qualcomm/sc7180/inc... File src/soc/qualcomm/sc7180/include/soc/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/35494/5/src/soc/qualcomm/sc7180/inc... PS5, Line 19: 0x14699000
number doesn't match the one below?
Ack
https://review.coreboot.org/c/coreboot/+/35494/5/src/soc/qualcomm/sc7180/inc... PS5, Line 35: REGION(bsram_reserved1, 0x14800000, 84K, 4K)
nit: Can we add a comment what it is reserved for? (I think I asked about this region on SDM845 alre […]
We are removing for now and if need to reserve it, will indicate for what reason.
https://review.coreboot.org/c/coreboot/+/35494/5/src/soc/qualcomm/sc7180/inc... PS5, Line 40: REGION(bsram_align1, 0x14838C00, 1K, 1K)
nit: No need to define regions for empty space, you can just leave it empty
Ack
https://review.coreboot.org/c/coreboot/+/35494/5/src/soc/qualcomm/sc7180/inc... PS5, Line 48: REGION(bsram_unused, 0x14853400, 0x1CC00, 1K)
nit: same here
Ack
https://review.coreboot.org/c/coreboot/+/35494/5/src/soc/qualcomm/sc7180/inc... PS5, Line 57: REGION(dram_reserved, 0x80900000, 0x200000, 0x1000)
nit: can we find better names to differentiate these two?
Done
https://review.coreboot.org/c/coreboot/+/35494/5/src/soc/qualcomm/sc7180/inc... PS5, Line 58: /* Various hardware/software subsystems make use of this area */
This comment looks like it's supposed to be two lines earlier?
Done
https://review.coreboot.org/c/coreboot/+/35494/5/src/soc/qualcomm/sc7180/inc... PS5, Line 61: RAMSTAGE(0x9F860000, 2M)
nit: with the recent addition of FIT booting code (not used by Chrome OS (yet), but by others) which […]
Done
https://review.coreboot.org/c/coreboot/+/35494/5/src/soc/qualcomm/sc7180/inc... File src/soc/qualcomm/sc7180/include/soc/symbols.h:
https://review.coreboot.org/c/coreboot/+/35494/5/src/soc/qualcomm/sc7180/inc... PS5, Line 25: DECLARE_REGION(el3_stack_canary);
Looks like this is a leftover that was already removed from SDM845 at some point?
Done
https://review.coreboot.org/c/coreboot/+/35494/5/src/soc/qualcomm/sc7180/uar... File src/soc/qualcomm/sc7180/uart_bitbang.c:
https://review.coreboot.org/c/coreboot/+/35494/5/src/soc/qualcomm/sc7180/uar... PS5, Line 21: #if 0
Can't commit stuff like this. […]
Done
https://review.coreboot.org/c/coreboot/+/35494/5/src/soc/qualcomm/sc7180/uar... PS5, Line 25: gpio_t uart_gpio = { 0 };
... […]
Done
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35494 )
Change subject: sc7180: initial SoC support ......................................................................
Patch Set 6:
Hi T.mike, did you try to upload a new patch set? You answered "Done" to a bunch of comments, but what you uploaded was still the same code as before.
Hello Alexander Couzens, Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35494
to look at the new patch set (#7).
Change subject: sc7180: Provide initial SoC support ......................................................................
sc7180: Provide initial SoC support
Change-Id: Iddcef560c1987486436b73ca1d5fc83cee2f713c Signed-off-by: T Michael Turney mturney@codeaurora.org --- A src/soc/qualcomm/sc7180/Kconfig A src/soc/qualcomm/sc7180/Makefile.inc A src/soc/qualcomm/sc7180/bootblock.c A src/soc/qualcomm/sc7180/cbmem.c A src/soc/qualcomm/sc7180/include/soc/addressmap.h A src/soc/qualcomm/sc7180/include/soc/gpio.h A src/soc/qualcomm/sc7180/include/soc/memlayout.ld A src/soc/qualcomm/sc7180/include/soc/mmu.h A src/soc/qualcomm/sc7180/include/soc/symbols.h A src/soc/qualcomm/sc7180/mmu.c A src/soc/qualcomm/sc7180/qclib.c A src/soc/qualcomm/sc7180/soc.c A src/soc/qualcomm/sc7180/spi.c A src/soc/qualcomm/sc7180/timer.c 14 files changed, 440 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/35494/7
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35494 )
Change subject: sc7180: Provide initial SoC support ......................................................................
Patch Set 7:
(3 comments)
https://review.coreboot.org/c/coreboot/+/35494/7/src/soc/qualcomm/sc7180/inc... File src/soc/qualcomm/sc7180/include/soc/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/35494/7/src/soc/qualcomm/sc7180/inc... PS7, Line 19: 0x146AE000 Uhh... still doesn't match the number below? (SSRAM_END is 0x146A6000)
https://review.coreboot.org/c/coreboot/+/35494/7/src/soc/qualcomm/sc7180/inc... PS7, Line 56: 384K nit: Should also be bumped to 16M (see my earlier comment)
https://review.coreboot.org/c/coreboot/+/35494/7/src/soc/qualcomm/sc7180/inc... File src/soc/qualcomm/sc7180/include/soc/symbols.h:
https://review.coreboot.org/c/coreboot/+/35494/7/src/soc/qualcomm/sc7180/inc... PS7, Line 21: ; nit: These aren't supposed to have a semicolon (see src/include/symbols.h).
mturney mturney has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35494 )
Change subject: sc7180: Provide initial SoC support ......................................................................
Patch Set 7:
(3 comments)
https://review.coreboot.org/c/coreboot/+/35494/7/src/soc/qualcomm/sc7180/inc... File src/soc/qualcomm/sc7180/include/soc/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/35494/7/src/soc/qualcomm/sc7180/inc... PS7, Line 19: 0x146AE000
Uhh... […]
Done
https://review.coreboot.org/c/coreboot/+/35494/7/src/soc/qualcomm/sc7180/inc... PS7, Line 56: 384K
nit: Should also be bumped to 16M (see my earlier comment)
Done
https://review.coreboot.org/c/coreboot/+/35494/7/src/soc/qualcomm/sc7180/inc... File src/soc/qualcomm/sc7180/include/soc/symbols.h:
https://review.coreboot.org/c/coreboot/+/35494/7/src/soc/qualcomm/sc7180/inc... PS7, Line 21: ;
nit: These aren't supposed to have a semicolon (see src/include/symbols.h).
Done
Hello Alexander Couzens, Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35494
to look at the new patch set (#8).
Change subject: sc7180: Provide initial SoC support ......................................................................
sc7180: Provide initial SoC support
Change-Id: Iddcef560c1987486436b73ca1d5fc83cee2f713c Signed-off-by: T Michael Turney mturney@codeaurora.org --- A src/soc/qualcomm/sc7180/Kconfig A src/soc/qualcomm/sc7180/Makefile.inc A src/soc/qualcomm/sc7180/bootblock.c A src/soc/qualcomm/sc7180/cbmem.c A src/soc/qualcomm/sc7180/include/soc/addressmap.h A src/soc/qualcomm/sc7180/include/soc/gpio.h A src/soc/qualcomm/sc7180/include/soc/memlayout.ld A src/soc/qualcomm/sc7180/include/soc/mmu.h A src/soc/qualcomm/sc7180/include/soc/symbols.h A src/soc/qualcomm/sc7180/mmu.c A src/soc/qualcomm/sc7180/qclib.c A src/soc/qualcomm/sc7180/soc.c A src/soc/qualcomm/sc7180/spi.c A src/soc/qualcomm/sc7180/timer.c 14 files changed, 441 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/35494/8
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35494 )
Change subject: sc7180: Provide initial SoC support ......................................................................
Patch Set 8: Code-Review+2
Alexander Couzens has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35494 )
Change subject: sc7180: Provide initial SoC support ......................................................................
Patch Set 8: Code-Review-1
Can you please add some documentation about the SoC to the docs/ directory? Also a brief description of the SoC to the commit message would be good. What kind of arm core does it use? What peripherals does it have?
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35494 )
Change subject: sc7180: Provide initial SoC support ......................................................................
Patch Set 8: -Code-Review
Can you please add some documentation about the SoC to the docs/ directory? Also a brief description of the SoC to the commit message would be good. What kind of arm core does it use? What peripherals does it have?
I'll leave it up to T.mike to see how much of this he can accommodate. Maybe we can add something about the peripherals for which drivers are already uploaded, like an overview of how the QUPs work? But please understand that there may be some information (e.g. probably CPU core specs) that Qualcomm doesn't want to publish at this time.
Alexander Couzens has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35494 )
Change subject: sc7180: Provide initial SoC support ......................................................................
Patch Set 8:
Patch Set 8: -Code-Review
Can you please add some documentation about the SoC to the docs/ directory? Also a brief description of the SoC to the commit message would be good. What kind of arm core does it use? What peripherals does it have?
I'll leave it up to T.mike to see how much of this he can accommodate. Maybe we can add something about the peripherals for which drivers are already uploaded, like an overview of how the QUPs work?
That would be great.
But please understand that there may be some information (e.g. probably CPU core specs) that Qualcomm doesn't want to publish at this time.
Sure. I know how it works.
mturney mturney has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35494 )
Change subject: sc7180: Provide initial SoC support ......................................................................
Patch Set 8:
Patch Set 8:
Patch Set 8: -Code-Review
Can you please add some documentation about the SoC to the docs/ directory? Also a brief description of the SoC to the commit message would be good. What kind of arm core does it use? What peripherals does it have?
I'll leave it up to T.mike to see how much of this he can accommodate. Maybe we can add something about the peripherals for which drivers are already uploaded, like an overview of how the QUPs work?
That would be great.
But please understand that there may be some information (e.g. probably CPU core specs) that Qualcomm doesn't want to publish at this time.
Sure. I know how it works.
By docs/ directory I assume you are referencing Documentation/ at top-level? A review of this folder's contents leaves me with these impressions: * current documentation is heavily x-86 centric * there is no SoC docs for an ARMv8 core * there is only single google board (dragonegg) and this is a how-to, not a what-is
I share this, not as an indictment so much as an explanation of what I will face when I bring this request up to my boss. The first response will be along the lines of either A) provide what other ARMv8 boards provide or B) what do other ARMv8 boards document?
As Julius has alluded to, my masters guard the corporate IP very closely and would probably suggest that technical info on sc7180 is already available in public domain.
I will discuss with Julius offline and add some detail to commit message, I doubt a new file under Documentation/ can be justified for the amount of info that is likely to be made available.
Hello Alexander Couzens, Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35494
to look at the new patch set (#9).
Change subject: sc7180: Provide initial SoC support ......................................................................
sc7180: Provide initial SoC support
Change-Id: Iddcef560c1987486436b73ca1d5fc83cee2f713c Signed-off-by: T Michael Turney mturney@codeaurora.org --- M Documentation/soc/index.md A Documentation/soc/qualcomm/index.md A Documentation/soc/qualcomm/sc7180/index.md A src/soc/qualcomm/sc7180/Kconfig A src/soc/qualcomm/sc7180/Makefile.inc A src/soc/qualcomm/sc7180/bootblock.c A src/soc/qualcomm/sc7180/cbmem.c A src/soc/qualcomm/sc7180/include/soc/addressmap.h A src/soc/qualcomm/sc7180/include/soc/gpio.h A src/soc/qualcomm/sc7180/include/soc/memlayout.ld A src/soc/qualcomm/sc7180/include/soc/mmu.h A src/soc/qualcomm/sc7180/include/soc/symbols.h A src/soc/qualcomm/sc7180/mmu.c A src/soc/qualcomm/sc7180/qclib.c A src/soc/qualcomm/sc7180/soc.c A src/soc/qualcomm/sc7180/spi.c A src/soc/qualcomm/sc7180/timer.c 17 files changed, 468 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/35494/9
mturney mturney has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35494 )
Change subject: sc7180: Provide initial SoC support ......................................................................
Patch Set 9:
I added a qualcomm tree under Documentation/soc and started to document the chip.
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35494 )
Change subject: sc7180: Provide initial SoC support ......................................................................
Patch Set 9: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35494 )
Change subject: sc7180: Provide initial SoC support ......................................................................
sc7180: Provide initial SoC support
Change-Id: Iddcef560c1987486436b73ca1d5fc83cee2f713c Signed-off-by: T Michael Turney mturney@codeaurora.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/35494 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Julius Werner jwerner@chromium.org --- M Documentation/soc/index.md A Documentation/soc/qualcomm/index.md A Documentation/soc/qualcomm/sc7180/index.md A src/soc/qualcomm/sc7180/Kconfig A src/soc/qualcomm/sc7180/Makefile.inc A src/soc/qualcomm/sc7180/bootblock.c A src/soc/qualcomm/sc7180/cbmem.c A src/soc/qualcomm/sc7180/include/soc/addressmap.h A src/soc/qualcomm/sc7180/include/soc/gpio.h A src/soc/qualcomm/sc7180/include/soc/memlayout.ld A src/soc/qualcomm/sc7180/include/soc/mmu.h A src/soc/qualcomm/sc7180/include/soc/symbols.h A src/soc/qualcomm/sc7180/mmu.c A src/soc/qualcomm/sc7180/qclib.c A src/soc/qualcomm/sc7180/soc.c A src/soc/qualcomm/sc7180/spi.c A src/soc/qualcomm/sc7180/timer.c 17 files changed, 468 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved
diff --git a/Documentation/soc/index.md b/Documentation/soc/index.md index fccddbd..1415c72 100644 --- a/Documentation/soc/index.md +++ b/Documentation/soc/index.md @@ -7,3 +7,4 @@ - [AMD](amd/index.md) - [Cavium](cavium/index.md) - [Intel](intel/index.md) +- [Qualcomm](qualcomm/index.md) diff --git a/Documentation/soc/qualcomm/index.md b/Documentation/soc/qualcomm/index.md new file mode 100644 index 0000000..5cd7981 --- /dev/null +++ b/Documentation/soc/qualcomm/index.md @@ -0,0 +1,7 @@ +# Qualcomm SOC-specific documentation + +This section contains documentation about coreboot on specific Qualcomm SOCs. + +## Platforms + +- [SC7180 series](sc7180/index.md) diff --git a/Documentation/soc/qualcomm/sc7180/index.md b/Documentation/soc/qualcomm/sc7180/index.md new file mode 100644 index 0000000..8f5d33d --- /dev/null +++ b/Documentation/soc/qualcomm/sc7180/index.md @@ -0,0 +1,19 @@ +# Qualcomm SC7180 documentation + +## SOC code + +The SOC folder contains functions for: +* MMU +* CLOCK +* GPIO +* QUPv3 FW (provides a bridge to serial interfaces) +* UART +* SPI-NOR +* AOP FW +* USB + +## Notes about the hardware + +The timer is used from the ARMv8 architecture specific code. + + diff --git a/src/soc/qualcomm/sc7180/Kconfig b/src/soc/qualcomm/sc7180/Kconfig new file mode 100644 index 0000000..2cd1d63 --- /dev/null +++ b/src/soc/qualcomm/sc7180/Kconfig @@ -0,0 +1,23 @@ + +config SOC_QUALCOMM_SC7180 + bool + default n + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select GENERIC_GPIO_LIB + select GENERIC_UDELAY + select HAVE_MONOTONIC_TIMER + select ARM64_USE_ARCH_TIMER + select SOC_QUALCOMM_COMMON + +if SOC_QUALCOMM_SC7180 + +config VBOOT + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_RETURN_FROM_VERSTAGE + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_BOOTBLOCK + +endif diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc new file mode 100644 index 0000000..08431f1 --- /dev/null +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -0,0 +1,36 @@ + +ifeq ($(CONFIG_SOC_QUALCOMM_SC7180),y) + +################################################################################ +bootblock-y += bootblock.c +bootblock-y += mmu.c +bootblock-y += timer.c +bootblock-y += spi.c + +################################################################################ +verstage-y += timer.c +verstage-y += spi.c + +################################################################################ +romstage-y += cbmem.c +romstage-y += timer.c +romstage-y += ../common/qclib.c +romstage-y += qclib.c +romstage-y += ../common/mmu.c +romstage-y += mmu.c +romstage-y += spi.c + +################################################################################ +ramstage-y += soc.c +ramstage-y += cbmem.c +ramstage-y += timer.c +ramstage-y += spi.c + +################################################################################ + +CPPFLAGS_common += -Isrc/soc/qualcomm/sc7180/include +CPPFLAGS_common += -Isrc/soc/qualcomm/common/include + +################################################################################ + +endif diff --git a/src/soc/qualcomm/sc7180/bootblock.c b/src/soc/qualcomm/sc7180/bootblock.c new file mode 100644 index 0000000..b9b8660 --- /dev/null +++ b/src/soc/qualcomm/sc7180/bootblock.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <soc/mmu.h> + +void bootblock_soc_init(void) +{ + sc7180_mmu_init(); +} diff --git a/src/soc/qualcomm/sc7180/cbmem.c b/src/soc/qualcomm/sc7180/cbmem.c new file mode 100644 index 0000000..597e369 --- /dev/null +++ b/src/soc/qualcomm/sc7180/cbmem.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> + +void *cbmem_top(void) +{ + return (void *)((uintptr_t)4 * GiB); +} diff --git a/src/soc/qualcomm/sc7180/include/soc/addressmap.h b/src/soc/qualcomm/sc7180/include/soc/addressmap.h new file mode 100644 index 0000000..93f0481 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/addressmap.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2018-2019 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_SC7180_ADDRESS_MAP_H_ +#define _SOC_QUALCOMM_SC7180_ADDRESS_MAP_H_ + +#include <stdint.h> + +#endif /* _SOC_QUALCOMM_SC7180_ADDRESS_MAP_H_ */ diff --git a/src/soc/qualcomm/sc7180/include/soc/gpio.h b/src/soc/qualcomm/sc7180/include/soc/gpio.h new file mode 100644 index 0000000..2b27672 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/gpio.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_SC7180_GPIO_H_ +#define _SOC_QUALCOMM_SC7180_GPIO_H_ + +#include <types.h> + +typedef struct { + u32 addr; +} gpio_t; + + +#endif /* _SOC_QUALCOMM_SC7180_GPIO_H_ */ diff --git a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld new file mode 100644 index 0000000..b2ee3b2 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <memlayout.h> +#include <arch/header.ld> + +/* SYSTEM_IMEM : 0x14680000 - 0x146AE000 */ +#define SSRAM_START(addr) SYMBOL(ssram, addr) +#define SSRAM_END(addr) SYMBOL(essram, addr) + +/* BOOT_IMEM : 0x14800000 - 0x14980000 */ +#define BSRAM_START(addr) SYMBOL(bsram, addr) +#define BSRAM_END(addr) SYMBOL(ebsram, addr) + +SECTIONS +{ + SSRAM_START(0x14680000) + OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 100K) + REGION(qcsdi, 0x14699000, 52K, 4K) + SSRAM_END(0x146AE000) + + BSRAM_START(0x14800000) + BOOTBLOCK(0x14815000, 40K) + PRERAM_CBFS_CACHE(0x1481F000, 70K) + PRERAM_CBMEM_CONSOLE(0x14830800, 32K) + TIMESTAMP(0x14838800, 1K) + TTB(0x14839000, 56K) + STACK(0x14847000, 16K) + VBOOT2_WORK(0x1484B000, 12K) + DMA_COHERENT(0x1484E000, 8K) + REGION(ddr_training, 0x14850000, 8K, 4K) + REGION(qclib_serial_log, 0x14852000, 4K, 4K) + REGION(ddr_information, 0x14853000, 1K, 1K) + REGION(dcb, 0x14870000, 16K, 4K) + REGION(pmic, 0x14874000, 44K, 4K) + REGION(limits_cfg, 0x1487F000, 4K, 4K) + REGION(qclib, 0x14880000, 512K, 4K) + BSRAM_END(0x14900000) + + DRAM_START(0x80000000) + /* Various hardware/software subsystems make use of this area */ + REGION(dram_soc, 0x80900000, 0x300000, 0x1000) + BL31(0x80C00000, 0x1A800000) + POSTRAM_CBFS_CACHE(0x9F800000, 16M) + RAMSTAGE(0xA0800000, 16M) +} diff --git a/src/soc/qualcomm/sc7180/include/soc/mmu.h b/src/soc/qualcomm/sc7180/include/soc/mmu.h new file mode 100644 index 0000000..735ce17 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/mmu.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_SC7180_MMU_H_ +#define _SOC_QUALCOMM_SC7180_MMU_H_ + +void sc7180_mmu_init(void); + +#endif /* _SOC_QUALCOMM_SC7180_MMU_H_ */ diff --git a/src/soc/qualcomm/sc7180/include/soc/symbols.h b/src/soc/qualcomm/sc7180/include/soc/symbols.h new file mode 100644 index 0000000..f379bb9 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/symbols.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_SC7180_SYMBOLS_H_ +#define _SOC_QUALCOMM_SC7180_SYMBOLS_H_ + +#include <symbols.h> + +DECLARE_REGION(ssram) +DECLARE_REGION(bsram) +DECLARE_REGION(dram_aop) +DECLARE_REGION(dram_soc) +DECLARE_REGION(dcb) +DECLARE_REGION(pmic) +DECLARE_REGION(limits_cfg) + +#endif /* _SOC_QUALCOMM_SC7180_SYMBOLS_H_ */ diff --git a/src/soc/qualcomm/sc7180/mmu.c b/src/soc/qualcomm/sc7180/mmu.c new file mode 100644 index 0000000..231b06f --- /dev/null +++ b/src/soc/qualcomm/sc7180/mmu.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <symbols.h> +#include <arch/mmu.h> +#include <arch/cache.h> +#include <soc/mmu.h> +#include <soc/mmu_common.h> +#include <soc/symbols.h> + +void sc7180_mmu_init(void) +{ + mmu_init(); + + mmu_config_range((void *)(4 * KiB), ((4UL * GiB) - (4 * KiB)), DEV_MEM); + mmu_config_range((void *)_ssram, REGION_SIZE(ssram), CACHED_RAM); + mmu_config_range((void *)_bsram, REGION_SIZE(bsram), CACHED_RAM); + mmu_config_range((void *)_dma_coherent, REGION_SIZE(dma_coherent), + UNCACHED_RAM); + + mmu_enable(); +} diff --git a/src/soc/qualcomm/sc7180/qclib.c b/src/soc/qualcomm/sc7180/qclib.c new file mode 100644 index 0000000..9c05452 --- /dev/null +++ b/src/soc/qualcomm/sc7180/qclib.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <fmap.h> +#include <console/console.h> +#include <soc/symbols.h> +#include <soc/qclib_common.h> + +int qclib_soc_blob_load(void) +{ + size_t size; + ssize_t ssize; + + /* Attempt to load PMICCFG Blob */ + size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/pmiccfg", + _pmic, REGION_SIZE(pmic), CBFS_TYPE_RAW); + if (!size) + return -1; + qclib_add_if_table_entry(QCLIB_TE_PMIC_SETTINGS, _pmic, size, 0); + + /* Attempt to load DCB Blob */ + size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/dcb", + _dcb, REGION_SIZE(dcb), CBFS_TYPE_RAW); + if (!size) + return -1; + qclib_add_if_table_entry(QCLIB_TE_DCB_SETTINGS, _dcb, size, 0); + + /* Attempt to load Limits Config Blob */ + ssize = fmap_read_area(QCLIB_FR_LIMITS_CFG_DATA, _limits_cfg, + REGION_SIZE(limits_cfg)); + if (ssize < 0) + return -1; + qclib_add_if_table_entry(QCLIB_TE_LIMITS_CFG_DATA, + _limits_cfg, ssize, 0); + + return 0; +} diff --git a/src/soc/qualcomm/sc7180/soc.c b/src/soc/qualcomm/sc7180/soc.c new file mode 100644 index 0000000..7003b39 --- /dev/null +++ b/src/soc/qualcomm/sc7180/soc.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <symbols.h> +#include <device/device.h> +#include <soc/mmu.h> +#include <soc/mmu_common.h> +#include <soc/symbols.h> + +static void soc_read_resources(struct device *dev) +{ + ram_resource(dev, 0, (uintptr_t)ddr_region->offset / KiB, + ddr_region->size / KiB); + reserved_ram_resource(dev, 1, (uintptr_t)_dram_soc / KiB, + REGION_SIZE(dram_soc) / KiB); +} + +static void soc_init(struct device *dev) +{ + +} + +static struct device_operations soc_ops = { + .read_resources = soc_read_resources, + .init = soc_init, +}; + +static void enable_soc_dev(struct device *dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_qualcomm_sc7180_ops = { + CHIP_NAME("SOC Qualcomm SC7180") + .enable_dev = enable_soc_dev, +}; diff --git a/src/soc/qualcomm/sc7180/spi.c b/src/soc/qualcomm/sc7180/spi.c new file mode 100644 index 0000000..5abb81a --- /dev/null +++ b/src/soc/qualcomm/sc7180/spi.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <spi-generic.h> +#include <spi_flash.h> + +static const struct spi_ctrlr spi_ctrlr; + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_ctrlr, + .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, + }, +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/soc/qualcomm/sc7180/timer.c b/src/soc/qualcomm/sc7180/timer.c new file mode 100644 index 0000000..5b78c1d --- /dev/null +++ b/src/soc/qualcomm/sc7180/timer.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <delay.h> +#include <arch/lib_helpers.h> +#include <commonlib/helpers.h> + +void init_timer(void) +{ + raw_write_cntfrq_el0(19200*KHz); +}
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Alexander Couzens (Code Review) -
Julius Werner (Code Review)
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mturney mturney (Code Review)
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Patrick Georgi (Code Review)