Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Karthik Ramasubramanian.
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56915 )
Change subject: mb/google/brya: set PL4 value dynamically for thermal
......................................................................
Patch Set 2:
(2 comments)
File src/mainboard/google/brya/variants/baseboard/brya/ramstage.c:
https://review.coreboot.org/c/coreboot/+/56915/comment/540a0176_1ceb0fb8
PS1, Line 29: struct soc_power_limits_config *soc_config;
: config_t *conf = config_of_soc();
: soc_config = conf->power_limits_config;
nit: this can go down below line 37, and be simplified to: […]
Ack
https://review.coreboot.org/c/coreboot/+/56915/comment/a99161ca_dcf174d4
PS1, Line 43: DPTF
DPTF does not control PL4, so I would drop that acronym here.
Done
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