[S] Change in coreboot[master]: soc/intel/alderlake/iomap: Fix the PCR BAR size on ADL-S

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69948 )

Change subject: soc/intel/alderlake/iomap: Fix the PCR BAR size on ADL-S
......................................................................

soc/intel/alderlake/iomap: Fix the PCR BAR size on ADL-S

According to ADL PCH BIOS specification (DOC# 630603) ADL-S PCH
uses a fixed SBREG_BAR of 256MiB starting at 0xe0000000.

Signed-off-by: Michał Żygowski 
Change-Id: Ied59a6dad8fb065dc3aeb6281bd32074aaa5e3b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69948
Tested-by: build bot (Jenkins) 
Reviewed-by: Eric Lai 
---
M src/soc/intel/alderlake/include/soc/iomap.h
1 file changed, 20 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Eric Lai: Looks good to me, approved

diff --git a/src/soc/intel/alderlake/include/soc/iomap.h b/src/soc/intel/alderlake/include/soc/iomap.h
index 6dd3bec..b451a72 100644
--- a/src/soc/intel/alderlake/include/soc/iomap.h
+++ b/src/soc/intel/alderlake/include/soc/iomap.h
@@ -123,6 +123,10 @@
 #define TCO_BASE_SIZE		0x20

#define P2SB_BAR		CONFIG_PCR_BASE_ADDRESS
+#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
+#define P2SB_SIZE		(256 * MiB)
+#else
 #define P2SB_SIZE		(16 * MiB)
+#endif

#endif