Change in coreboot[master]: soc/intel/denverton_ns: Use common SMBus support code

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59469 )

Change subject: soc/intel/denverton_ns: Use common SMBus support code
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soc/intel/denverton_ns: Use common SMBus support code

Change-Id: I233d198b894f10fbf0042a5023ae8a9c14136513
Signed-off-by: Kyösti Mälkki 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59469
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
---
M src/soc/intel/common/block/smbus/smbus.c
M src/soc/intel/denverton_ns/Kconfig
M src/soc/intel/denverton_ns/include/soc/pci_devs.h
M src/soc/intel/denverton_ns/include/soc/smbus.h
4 files changed, 6 insertions(+), 23 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c
index 4a46143..d0eb9ce 100644
--- a/src/soc/intel/common/block/smbus/smbus.c
+++ b/src/soc/intel/common/block/smbus/smbus.c
@@ -91,6 +91,7 @@
    PCI_DEVICE_ID_INTEL_ADP_P_SMBUS,
    PCI_DEVICE_ID_INTEL_ADP_S_SMBUS,
    PCI_DEVICE_ID_INTEL_ADP_M_SMBUS,
+	PCI_DEVICE_ID_INTEL_DENVERTON_SMBUS_LEGACY,
    0
 };

diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig
index 0643384..09c1408 100644
--- a/src/soc/intel/denverton_ns/Kconfig
+++ b/src/soc/intel/denverton_ns/Kconfig
@@ -34,6 +34,8 @@
    select SOC_INTEL_COMMON_BLOCK_FAST_SPI
    select SOC_INTEL_COMMON_BLOCK_GPIO
    select SOC_INTEL_COMMON_BLOCK_PCR
+	select SOC_INTEL_COMMON_BLOCK_SMBUS
+	select SOUTHBRIDGE_INTEL_COMMON_SMBUS
    select TSC_MONOTONIC_TIMER
    select TSC_SYNC_MFENCE
    select UDELAY_TSC
diff --git a/src/soc/intel/denverton_ns/include/soc/pci_devs.h b/src/soc/intel/denverton_ns/include/soc/pci_devs.h
index 0cb4c98..9fa38e4 100644
--- a/src/soc/intel/denverton_ns/include/soc/pci_devs.h
+++ b/src/soc/intel/denverton_ns/include/soc/pci_devs.h
@@ -139,9 +139,11 @@
 #define PCH_DEV_SLOT_LPC 0x1f
 #define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0)
 #define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2)
+#define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 4)
 #define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5)
 #define PCH_DEV_LPC _PCH_DEV(LPC, 0)
 #define PCH_DEV_SPI _PCH_DEV(LPC, 5)
+#define PCH_DEV_SMBUS _PCH_DEV(LPC, 4)

/* VT-d support value to match FSP settings */
 /* "PCH IOAPIC Config" */
diff --git a/src/soc/intel/denverton_ns/include/soc/smbus.h b/src/soc/intel/denverton_ns/include/soc/smbus.h
index e51d8a7..8dba9ad 100644
--- a/src/soc/intel/denverton_ns/include/soc/smbus.h
+++ b/src/soc/intel/denverton_ns/include/soc/smbus.h
@@ -17,29 +17,7 @@
 #define TCOBASE_EN (1 << 8)
 #define TCOBASE_LOCK (1 << 0)

-/* SMBus I/O bits. */
-#define SMBHSTSTAT 0x0
-#define HST_HBSY (1 << 0)
-#define HST_INTR (1 << 1)
-#define HST_DERR (1 << 2)
-#define HST_BERR (1 << 3)
-#define HST_BYTE_DONE_STS (1 << 7)
-#define HST_HSTS_ALL 0xFF
-#define SMBHSTCTL 0x2
-#define HST_LAST_BYTE (1 << 5)
-#define HST_START (1 << 6)
-#define HST_CMD_IIC_READ 0x18
-#define HST_READ 0x01 // RW
-#define SMBHSTCMD 0x3
-#define SMBXMITADD 0x4
-#define SMBHSTDAT0 0x5
-#define SMBHSTDAT1 0x6
-#define SMBBLKDAT 0x7
-#define SMBTRNSADD 0x9
-#define SMBSLVDATA 0xa
-#define SMBHSTAUXC 0xd
-#define SMLINK_PIN_CTL 0xe
-#define SMBUS_PIN_CTL 0xf
+#define SMBUS_SLAVE_ADDR		0x44

/*
  * SMBus Private Config Registers (PID:SMB)