Change in ...coreboot[master]: {northbridge, soc, southbridge}/intel: Make use of generic set_subsys...
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31985
Change subject: {northbridge, soc, southbridge}/intel: Make use of generic set_subsystem() ......................................................................
{northbridge, soc, southbridge}/intel: Make use of generic set_subsystem()
This patch removes all local definitions of sub_system functions and make use of common generic pci_dev_set_subsystem() from PCI bridge and Cardbus devices as well.
Change-Id: Ibe0905559943796adf5c89826cc0a99ed077ec63 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/northbridge/intel/sandybridge/pcie.c M src/soc/intel/broadwell/pcie.c M src/soc/intel/common/block/pcie/pcie.c M src/southbridge/intel/bd82x6x/pcie.c M src/southbridge/intel/i82801gx/pcie.c M src/southbridge/intel/i82801ix/pcie.c M src/southbridge/intel/i82801jx/pcie.c M src/southbridge/intel/lynxpoint/pcie.c M src/southbridge/ricoh/rl5c476/rl5c476.c M src/southbridge/ti/pci1x2x/pci1x2x.c 10 files changed, 11 insertions(+), 109 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/31985/1
diff --git a/src/northbridge/intel/sandybridge/pcie.c b/src/northbridge/intel/sandybridge/pcie.c index 16bc314..344cd80 100644 --- a/src/northbridge/intel/sandybridge/pcie.c +++ b/src/northbridge/intel/sandybridge/pcie.c @@ -65,20 +65,8 @@ } #endif
-static void -pcie_set_subsystem(struct device *dev, unsigned int ven, unsigned int device) -{ - /* NOTE: This is not the default position! */ - if (!ven || !device) - pci_write_config32(dev, 0x94, - pci_read_config32(dev, 0)); - else - pci_write_config32(dev, 0x94, - ((device & 0xffff) << 16) | (ven & 0xffff)); -} - static struct pci_operations pci_ops = { - .set_subsystem = pcie_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, };
static struct device_operations device_ops = { diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index 32135ee..472e8da 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -649,16 +649,6 @@ root_port_commit_config(); }
-static void pcie_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - /* NOTE: This is not the default position! */ - if (!vendor || !device) - pci_write_config32(dev, 0x94, pci_read_config32(dev, 0)); - else - pci_write_config32(dev, 0x94, (device << 16) | vendor); -} - static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int off) { /* Set max snoop and non-snoop latency for Broadwell */ @@ -666,7 +656,7 @@ }
static struct pci_operations pcie_ops = { - .set_subsystem = pcie_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, .set_L1_ss_latency = pcie_set_L1_ss_max_latency, };
diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index 8295765..d74b098 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -25,8 +25,6 @@ #define PCIE_LTR_MAX_NO_SNOOP_LATENCY_VALUE 0x1003 /* Latency tolerance reporting, max snoop latency value 3.14ms */ #define PCIE_LTR_MAX_SNOOP_LATENCY_VALUE 0x1003 -/* PCI-E Sub-System ID */ -#define PCIE_SUBSYSTEM_VENDOR_ID 0x94
static void pch_pcie_init(struct device *dev) { @@ -72,16 +70,9 @@ PCIE_LTR_MAX_SNOOP_LATENCY_VALUE); }
-static void pcie_dev_set_subsystem(struct device *dev, - unsigned int vendor, unsigned int device) -{ - pci_write_config32(dev, PCIE_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); -} - static struct pci_operations pcie_ops = { .set_L1_ss_latency = pcie_set_L1_ss_max_latency, - .set_subsystem = pcie_dev_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, };
static struct device_operations device_ops = { diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 39c53e8..0bc75b5 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -306,21 +306,8 @@ return NULL; }
-static void pcie_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - /* NOTE: This is not the default position! */ - if (!vendor || !device) { - pci_write_config32(dev, 0x94, - pci_read_config32(dev, 0)); - } else { - pci_write_config32(dev, 0x94, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations pci_ops = { - .set_subsystem = pcie_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, };
static struct device_operations device_ops = { diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index 9446527..3e5dbc3 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -252,22 +252,8 @@ root_port_commit_config(dev); }
- -static void pcie_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) -{ - /* NOTE: This is not the default position! */ - if (!vendor || !device) { - pci_write_config32(dev, 0x94, - pci_read_config32(dev, 0)); - } else { - pci_write_config32(dev, 0x94, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations pci_ops = { - .set_subsystem = pcie_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, };
static struct device_operations device_ops = { diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c index a36fdc6..3b90ce6 100644 --- a/src/southbridge/intel/i82801ix/pcie.c +++ b/src/southbridge/intel/i82801ix/pcie.c @@ -95,19 +95,6 @@ } }
-static void pcie_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - /* NOTE: 0x94 is not the default position! */ - if (!vendor || !device) { - pci_write_config32(dev, 0x94, - pci_read_config32(dev, 0)); - } else { - pci_write_config32(dev, 0x94, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static void pch_pciexp_scan_bridge(struct device *dev) { struct southbridge_intel_i82801ix_config *config = dev->chip_info; @@ -121,7 +108,7 @@ }
static struct pci_operations pci_ops = { - .set_subsystem = pcie_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, };
static struct device_operations device_ops = { diff --git a/src/southbridge/intel/i82801jx/pcie.c b/src/southbridge/intel/i82801jx/pcie.c index fb90cd9..84b2b6a 100644 --- a/src/southbridge/intel/i82801jx/pcie.c +++ b/src/southbridge/intel/i82801jx/pcie.c @@ -95,19 +95,6 @@ } }
-static void pcie_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - /* NOTE: 0x94 is not the default position! */ - if (!vendor || !device) { - pci_write_config32(dev, 0x94, - pci_read_config32(dev, 0)); - } else { - pci_write_config32(dev, 0x94, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static void pch_pciexp_scan_bridge(struct device *dev) { struct southbridge_intel_i82801jx_config *config = dev->chip_info; @@ -121,7 +108,7 @@ }
static struct pci_operations pci_ops = { - .set_subsystem = pcie_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, };
static struct device_operations device_ops = { diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 695abf2..2a8b44e 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -727,21 +727,8 @@ root_port_commit_config(); }
-static void pcie_set_subsystem(struct device *dev, unsigned vendor, - unsigned device) -{ - /* NOTE: This is not the default position! */ - if (!vendor || !device) { - pci_write_config32(dev, 0x94, - pci_read_config32(dev, 0)); - } else { - pci_write_config32(dev, 0x94, - ((device & 0xffff) << 16) | (vendor & 0xffff)); - } -} - static struct pci_operations pci_ops = { - .set_subsystem = pcie_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, };
static struct device_operations device_ops = { diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c index 4d8b6e6..c94722c 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.c +++ b/src/southbridge/ricoh/rl5c476/rl5c476.c @@ -200,8 +200,8 @@ /* Enable subsystem id register writes */ pci_write_config16(dev, 0x82, miscreg | 0x40);
- pci_write_config16(dev, 0x40, vendor); - pci_write_config16(dev, 0x42, device); + pci_dev_set_subsystem(dev, vendor, device); + /* restore original contents */ pci_write_config16(dev, 0x82, miscreg); } diff --git a/src/southbridge/ti/pci1x2x/pci1x2x.c b/src/southbridge/ti/pci1x2x/pci1x2x.c index f84d866..bfb5ab9 100644 --- a/src/southbridge/ti/pci1x2x/pci1x2x.c +++ b/src/southbridge/ti/pci1x2x/pci1x2x.c @@ -46,8 +46,7 @@ * to the sub-vendor/device ids at 40 and 42. */ pci_write_config32(dev, 0x80, pci_read_config32(dev, 0x080) & ~0x10); - pci_write_config16(dev, 0x40, vendor); - pci_write_config16(dev, 0x42, device); + pci_dev_set_subsystem(dev, vendor, device); pci_write_config32(dev, 0x80, pci_read_config32(dev, 0x80) | 0x10); }
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31985
to look at the new patch set (#2).
Change subject: {northbridge, soc, southbridge}/intel: Make use of generic set_subsystem() ......................................................................
{northbridge, soc, southbridge}/intel: Make use of generic set_subsystem()
This patch removes all local definitions of sub_system functions and make use of common generic pci_dev_set_subsystem() from PCI bridge and Cardbus devices as well.
Change-Id: I5fbed39ed448baf11f0e0786ce0ee94741d57237 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/northbridge/intel/sandybridge/pcie.c M src/soc/intel/broadwell/pcie.c M src/soc/intel/common/block/pcie/pcie.c M src/southbridge/intel/bd82x6x/pcie.c M src/southbridge/intel/i82801gx/pcie.c M src/southbridge/intel/i82801ix/pcie.c M src/southbridge/intel/i82801jx/pcie.c M src/southbridge/intel/lynxpoint/pcie.c M src/southbridge/ricoh/rl5c476/rl5c476.c M src/southbridge/ti/pci1x2x/pci1x2x.c 10 files changed, 11 insertions(+), 109 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/31985/2
Subrata Banik has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/31985 )
Change subject: {northbridge, soc, southbridge}/intel: Make use of generic set_subsystem() ......................................................................
Abandoned
-
Subrata Banik (Code Review)