Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31304
Change subject: device/pci_ops: Move questionable pci_locate() variants ......................................................................
device/pci_ops: Move questionable pci_locate() variants
These are defined for __SIMPLE_DEVICE__ when PCI enumeration has not happened yet. These should not really try to probe devices other than those on bus 0.
It's hard to track but there maybe cases of southbridge being located on bus 2 and available for configuration, so I rather leave the code unchanged. Just move these out of arch/io.h because they cause build failures if one attempts to include <arch/pci_ops.h> before <arch/io.h>.
There are two direct copies for ROMCC bootblocks to avoid inlining them elsewhere.
Change-Id: Ida2919a5d83fe5ea89284ffbd8ead382e4312524 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/arch/x86/include/arch/io.h M src/device/pci_early.c M src/include/device/pci.h M src/southbridge/amd/amd8111/bootblock.c M src/southbridge/amd/sb700/early_setup.c M src/southbridge/broadcom/bcm5785/bootblock.c M src/southbridge/intel/i82371eb/bootblock.c M src/southbridge/intel/i82371eb/early_pm.c M src/southbridge/intel/i82371eb/early_smbus.c 9 files changed, 82 insertions(+), 45 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/31304/1
diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 71e3ba0..4b4a178 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -205,10 +205,6 @@
#ifdef __SIMPLE_DEVICE__
-#define PCI_ID(VENDOR_ID, DEVICE_ID) \ - ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) - - #define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC))
#include <arch/pci_io_cfg.h> @@ -268,47 +264,6 @@ pci_io_write_config32(dev, where, value); }
-static inline pci_devfn_t pci_io_locate_device(unsigned int pci_id, - pci_devfn_t dev) -{ - for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) { - unsigned int id; - id = pci_io_read_config32(dev, 0); - if (id == pci_id) - return dev; - } - return PCI_DEV_INVALID; -} - -static inline pci_devfn_t pci_locate_device(unsigned int pci_id, - pci_devfn_t dev) -{ - for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) { - unsigned int id; - id = pci_read_config32(dev, 0); - if (id == pci_id) - return dev; - } - return PCI_DEV_INVALID; -} - -static inline pci_devfn_t pci_locate_device_on_bus(unsigned int pci_id, - unsigned int bus) -{ - pci_devfn_t dev, last; - - dev = PCI_DEV(bus, 0, 0); - last = PCI_DEV(bus, 31, 7); - - for (; dev <= last; dev += PCI_DEV(0, 0, 1)) { - unsigned int id; - id = pci_read_config32(dev, 0); - if (id == pci_id) - return dev; - } - return PCI_DEV_INVALID; -} - /* Generic functions for pnp devices */ static __always_inline void pnp_write_config( pnp_devfn_t dev, uint8_t reg, uint8_t value) diff --git a/src/device/pci_early.c b/src/device/pci_early.c index 9086e64..ea2ebd5 100644 --- a/src/device/pci_early.c +++ b/src/device/pci_early.c @@ -165,3 +165,34 @@
pci_early_mmio_window(p2p_bridge, CONFIG_EARLY_PCI_MMIO_BASE, 0x4000); } + +/* FIXME: A lot of issues using the following, please avoid. + * Assumes 256 PCI busses, scans them all even when PCI bridges are still + * disabled. Probes all functions even if 0 is not present. + */ +pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev) +{ + for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) { + unsigned int id; + id = pci_read_config32(dev, 0); + if (id == pci_id) + return dev; + } + return PCI_DEV_INVALID; +} + +pci_devfn_t pci_locate_device_on_bus(unsigned int pci_id, unsigned int bus) +{ + pci_devfn_t dev, last; + + dev = PCI_DEV(bus, 0, 0); + last = PCI_DEV(bus, 31, 7); + + for (; dev <= last; dev += PCI_DEV(0, 0, 1)) { + unsigned int id; + id = pci_read_config32(dev, 0); + if (id == pci_id) + return dev; + } + return PCI_DEV_INVALID; +} diff --git a/src/include/device/pci.h b/src/include/device/pci.h index f0724e0f..71d6b20 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -133,6 +133,12 @@ return pops; }
+#define PCI_ID(VENDOR_ID, DEVICE_ID) \ + ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) + +pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev); +pci_devfn_t pci_locate_device_on_bus(unsigned int pci_id, unsigned int bus); + #ifdef __SIMPLE_DEVICE__ unsigned int pci_find_next_capability(pci_devfn_t dev, unsigned int cap, unsigned int last); diff --git a/src/southbridge/amd/amd8111/bootblock.c b/src/southbridge/amd/amd8111/bootblock.c index 2c722c8..7cbc141 100644 --- a/src/southbridge/amd/amd8111/bootblock.c +++ b/src/southbridge/amd/amd8111/bootblock.c @@ -17,6 +17,18 @@ #include <stdint.h> #include <arch/io.h> #include <device/pci_ids.h> +#include <device/pci_type.h> + +static pci_devfn_t pci_io_locate_device(unsigned int pci_id, pci_devfn_t dev) +{ + for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) { + unsigned int id; + id = pci_io_read_config32(dev, 0); + if (id == pci_id) + return dev; + } + return PCI_DEV_INVALID; +}
/* Enable 5MB ROM access at 0xFFB00000 - 0xFFFFFFFF. */ static void amd8111_enable_rom(void) diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 70cf340..167986f 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -22,6 +22,7 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/msr.h> +#include <device/pci.h>
#include <reset.h> #include "sb700.h" diff --git a/src/southbridge/broadcom/bcm5785/bootblock.c b/src/southbridge/broadcom/bcm5785/bootblock.c index 2861ff0..62b20a3 100644 --- a/src/southbridge/broadcom/bcm5785/bootblock.c +++ b/src/southbridge/broadcom/bcm5785/bootblock.c @@ -17,6 +17,21 @@ #include <stdint.h> #include <arch/io.h> #include <device/pci_ids.h> +#include <device/pci_type.h> + +#define PCI_ID(VENDOR_ID, DEVICE_ID) \ + ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) + +static pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev) +{ + for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) { + unsigned int id; + id = pci_read_config32(dev, 0); + if (id == pci_id) + return dev; + } + return PCI_DEV_INVALID; +}
/* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ static void bcm5785_enable_rom(void) diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c index c59343d..38b797d 100644 --- a/src/southbridge/intel/i82371eb/bootblock.c +++ b/src/southbridge/intel/i82371eb/bootblock.c @@ -17,8 +17,23 @@ #include <stdint.h> #include <arch/io.h> #include <device/pci_ids.h> +#include <device/pci_type.h> #include "i82371eb.h"
+#define PCI_ID(VENDOR_ID, DEVICE_ID) \ + ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) + +static pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev) +{ + for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) { + unsigned int id; + id = pci_read_config32(dev, 0); + if (id == pci_id) + return dev; + } + return PCI_DEV_INVALID; +} + static void bootblock_southbridge_init(void) { u16 reg16; diff --git a/src/southbridge/intel/i82371eb/early_pm.c b/src/southbridge/intel/i82371eb/early_pm.c index 8ae7669..720cb0d 100644 --- a/src/southbridge/intel/i82371eb/early_pm.c +++ b/src/southbridge/intel/i82371eb/early_pm.c @@ -16,6 +16,7 @@
#include <stdint.h> #include <arch/io.h> +#include <device/pci.h> #include <device/pci_def.h> #include <device/pci_ids.h> #include "i82371eb.h" diff --git a/src/southbridge/intel/i82371eb/early_smbus.c b/src/southbridge/intel/i82371eb/early_smbus.c index de16717..4e91c0a 100644 --- a/src/southbridge/intel/i82371eb/early_smbus.c +++ b/src/southbridge/intel/i82371eb/early_smbus.c @@ -16,6 +16,7 @@
#include <stdint.h> #include <arch/io.h> +#include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_def.h> #include <southbridge/intel/common/smbus.h>
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31304
to look at the new patch set (#2).
Change subject: device/pci_ops: Move questionable pci_locate() variants ......................................................................
device/pci_ops: Move questionable pci_locate() variants
These are defined for __SIMPLE_DEVICE__ when PCI enumeration has not happened yet. These should not really try to probe devices other than those on bus 0.
It's hard to track but there maybe cases of southbridge being located on bus 2 and available for configuration, so I rather leave the code unchanged. Just move these out of arch/io.h because they cause build failures if one attempts to include <arch/pci_ops.h> before <arch/io.h>.
There are two direct copies for ROMCC bootblocks to avoid inlining them elsewhere.
Change-Id: Ida2919a5d83fe5ea89284ffbd8ead382e4312524 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/arch/x86/include/arch/io.h M src/device/pci_early.c M src/include/device/pci.h M src/southbridge/amd/amd8111/bootblock.c M src/southbridge/amd/sb700/early_setup.c M src/southbridge/broadcom/bcm5785/bootblock.c M src/southbridge/intel/i82371eb/bootblock.c M src/southbridge/intel/i82371eb/early_pm.c M src/southbridge/intel/i82371eb/early_smbus.c M src/southbridge/nvidia/ck804/early_smbus.c M src/southbridge/nvidia/mcp55/early_smbus.c 11 files changed, 87 insertions(+), 45 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/31304/2
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31304
to look at the new patch set (#3).
Change subject: device/pci_ops: Move questionable pci_locate() variants ......................................................................
device/pci_ops: Move questionable pci_locate() variants
These are defined for __SIMPLE_DEVICE__ when PCI enumeration has not happened yet. These should not really try to probe devices other than those on bus 0.
It's hard to track but there maybe cases of southbridge being located on bus 2 and available for configuration, so I rather leave the code unchanged. Just move these out of arch/io.h because they cause build failures if one attempts to include <arch/pci_ops.h> before <arch/io.h>.
There are two direct copies for ROMCC bootblocks to avoid inlining them elsewhere.
Change-Id: Ida2919a5d83fe5ea89284ffbd8ead382e4312524 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/arch/x86/include/arch/io.h M src/device/pci_early.c M src/include/device/pci.h M src/southbridge/amd/amd8111/bootblock.c M src/southbridge/amd/amd8111/reset.c M src/southbridge/amd/sb700/early_setup.c M src/southbridge/broadcom/bcm5785/bootblock.c M src/southbridge/intel/i82371eb/bootblock.c M src/southbridge/intel/i82371eb/early_pm.c M src/southbridge/intel/i82371eb/early_smbus.c M src/southbridge/nvidia/ck804/early_smbus.c M src/southbridge/nvidia/mcp55/early_smbus.c 12 files changed, 88 insertions(+), 45 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/31304/3
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31304 )
Change subject: device/pci_ops: Move questionable pci_locate() variants ......................................................................
Patch Set 3: Code-Review+2
Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31304 )
Change subject: device/pci_ops: Move questionable pci_locate() variants ......................................................................
device/pci_ops: Move questionable pci_locate() variants
These are defined for __SIMPLE_DEVICE__ when PCI enumeration has not happened yet. These should not really try to probe devices other than those on bus 0.
It's hard to track but there maybe cases of southbridge being located on bus 2 and available for configuration, so I rather leave the code unchanged. Just move these out of arch/io.h because they cause build failures if one attempts to include <arch/pci_ops.h> before <arch/io.h>.
There are two direct copies for ROMCC bootblocks to avoid inlining them elsewhere.
Change-Id: Ida2919a5d83fe5ea89284ffbd8ead382e4312524 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/31304 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/arch/x86/include/arch/io.h M src/device/pci_early.c M src/include/device/pci.h M src/southbridge/amd/amd8111/bootblock.c M src/southbridge/amd/amd8111/reset.c M src/southbridge/amd/sb700/early_setup.c M src/southbridge/broadcom/bcm5785/bootblock.c M src/southbridge/intel/i82371eb/bootblock.c M src/southbridge/intel/i82371eb/early_pm.c M src/southbridge/intel/i82371eb/early_smbus.c M src/southbridge/nvidia/ck804/early_smbus.c M src/southbridge/nvidia/mcp55/early_smbus.c 12 files changed, 88 insertions(+), 45 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 71e3ba0..4b4a178 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -205,10 +205,6 @@
#ifdef __SIMPLE_DEVICE__
-#define PCI_ID(VENDOR_ID, DEVICE_ID) \ - ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) - - #define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC))
#include <arch/pci_io_cfg.h> @@ -268,47 +264,6 @@ pci_io_write_config32(dev, where, value); }
-static inline pci_devfn_t pci_io_locate_device(unsigned int pci_id, - pci_devfn_t dev) -{ - for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) { - unsigned int id; - id = pci_io_read_config32(dev, 0); - if (id == pci_id) - return dev; - } - return PCI_DEV_INVALID; -} - -static inline pci_devfn_t pci_locate_device(unsigned int pci_id, - pci_devfn_t dev) -{ - for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) { - unsigned int id; - id = pci_read_config32(dev, 0); - if (id == pci_id) - return dev; - } - return PCI_DEV_INVALID; -} - -static inline pci_devfn_t pci_locate_device_on_bus(unsigned int pci_id, - unsigned int bus) -{ - pci_devfn_t dev, last; - - dev = PCI_DEV(bus, 0, 0); - last = PCI_DEV(bus, 31, 7); - - for (; dev <= last; dev += PCI_DEV(0, 0, 1)) { - unsigned int id; - id = pci_read_config32(dev, 0); - if (id == pci_id) - return dev; - } - return PCI_DEV_INVALID; -} - /* Generic functions for pnp devices */ static __always_inline void pnp_write_config( pnp_devfn_t dev, uint8_t reg, uint8_t value) diff --git a/src/device/pci_early.c b/src/device/pci_early.c index 9086e64..ea2ebd5 100644 --- a/src/device/pci_early.c +++ b/src/device/pci_early.c @@ -165,3 +165,34 @@
pci_early_mmio_window(p2p_bridge, CONFIG_EARLY_PCI_MMIO_BASE, 0x4000); } + +/* FIXME: A lot of issues using the following, please avoid. + * Assumes 256 PCI busses, scans them all even when PCI bridges are still + * disabled. Probes all functions even if 0 is not present. + */ +pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev) +{ + for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) { + unsigned int id; + id = pci_read_config32(dev, 0); + if (id == pci_id) + return dev; + } + return PCI_DEV_INVALID; +} + +pci_devfn_t pci_locate_device_on_bus(unsigned int pci_id, unsigned int bus) +{ + pci_devfn_t dev, last; + + dev = PCI_DEV(bus, 0, 0); + last = PCI_DEV(bus, 31, 7); + + for (; dev <= last; dev += PCI_DEV(0, 0, 1)) { + unsigned int id; + id = pci_read_config32(dev, 0); + if (id == pci_id) + return dev; + } + return PCI_DEV_INVALID; +} diff --git a/src/include/device/pci.h b/src/include/device/pci.h index f0724e0f..71d6b20 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -133,6 +133,12 @@ return pops; }
+#define PCI_ID(VENDOR_ID, DEVICE_ID) \ + ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) + +pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev); +pci_devfn_t pci_locate_device_on_bus(unsigned int pci_id, unsigned int bus); + #ifdef __SIMPLE_DEVICE__ unsigned int pci_find_next_capability(pci_devfn_t dev, unsigned int cap, unsigned int last); diff --git a/src/southbridge/amd/amd8111/bootblock.c b/src/southbridge/amd/amd8111/bootblock.c index 2c722c8..0abd999 100644 --- a/src/southbridge/amd/amd8111/bootblock.c +++ b/src/southbridge/amd/amd8111/bootblock.c @@ -17,6 +17,21 @@ #include <stdint.h> #include <arch/io.h> #include <device/pci_ids.h> +#include <device/pci_type.h> + +#define PCI_ID(VENDOR_ID, DEVICE_ID) \ + ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) + +static pci_devfn_t pci_io_locate_device(unsigned int pci_id, pci_devfn_t dev) +{ + for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) { + unsigned int id; + id = pci_io_read_config32(dev, 0); + if (id == pci_id) + return dev; + } + return PCI_DEV_INVALID; +}
/* Enable 5MB ROM access at 0xFFB00000 - 0xFFFFFFFF. */ static void amd8111_enable_rom(void) diff --git a/src/southbridge/amd/amd8111/reset.c b/src/southbridge/amd/amd8111/reset.c index 41d9880..62ae99e 100644 --- a/src/southbridge/amd/amd8111/reset.c +++ b/src/southbridge/amd/amd8111/reset.c @@ -16,6 +16,7 @@
#include <arch/io.h> #include <reset.h> +#include <device/pci.h> #include <device/pci_ids.h>
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 70cf340..167986f 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -22,6 +22,7 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/msr.h> +#include <device/pci.h>
#include <reset.h> #include "sb700.h" diff --git a/src/southbridge/broadcom/bcm5785/bootblock.c b/src/southbridge/broadcom/bcm5785/bootblock.c index 2861ff0..62b20a3 100644 --- a/src/southbridge/broadcom/bcm5785/bootblock.c +++ b/src/southbridge/broadcom/bcm5785/bootblock.c @@ -17,6 +17,21 @@ #include <stdint.h> #include <arch/io.h> #include <device/pci_ids.h> +#include <device/pci_type.h> + +#define PCI_ID(VENDOR_ID, DEVICE_ID) \ + ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) + +static pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev) +{ + for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) { + unsigned int id; + id = pci_read_config32(dev, 0); + if (id == pci_id) + return dev; + } + return PCI_DEV_INVALID; +}
/* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ static void bcm5785_enable_rom(void) diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c index c59343d..38b797d 100644 --- a/src/southbridge/intel/i82371eb/bootblock.c +++ b/src/southbridge/intel/i82371eb/bootblock.c @@ -17,8 +17,23 @@ #include <stdint.h> #include <arch/io.h> #include <device/pci_ids.h> +#include <device/pci_type.h> #include "i82371eb.h"
+#define PCI_ID(VENDOR_ID, DEVICE_ID) \ + ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) + +static pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev) +{ + for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) { + unsigned int id; + id = pci_read_config32(dev, 0); + if (id == pci_id) + return dev; + } + return PCI_DEV_INVALID; +} + static void bootblock_southbridge_init(void) { u16 reg16; diff --git a/src/southbridge/intel/i82371eb/early_pm.c b/src/southbridge/intel/i82371eb/early_pm.c index 8ae7669..720cb0d 100644 --- a/src/southbridge/intel/i82371eb/early_pm.c +++ b/src/southbridge/intel/i82371eb/early_pm.c @@ -16,6 +16,7 @@
#include <stdint.h> #include <arch/io.h> +#include <device/pci.h> #include <device/pci_def.h> #include <device/pci_ids.h> #include "i82371eb.h" diff --git a/src/southbridge/intel/i82371eb/early_smbus.c b/src/southbridge/intel/i82371eb/early_smbus.c index de16717..4e91c0a 100644 --- a/src/southbridge/intel/i82371eb/early_smbus.c +++ b/src/southbridge/intel/i82371eb/early_smbus.c @@ -16,6 +16,7 @@
#include <stdint.h> #include <arch/io.h> +#include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_def.h> #include <southbridge/intel/common/smbus.h> diff --git a/src/southbridge/nvidia/ck804/early_smbus.c b/src/southbridge/nvidia/ck804/early_smbus.c index 51e200b..f7bddbf 100644 --- a/src/southbridge/nvidia/ck804/early_smbus.c +++ b/src/southbridge/nvidia/ck804/early_smbus.c @@ -17,6 +17,7 @@ #include <stdint.h> #include <arch/io.h> #include <console/console.h> +#include <device/pci.h> #include <device/pci_def.h> #include <device/pci_ids.h>
diff --git a/src/southbridge/nvidia/mcp55/early_smbus.c b/src/southbridge/nvidia/mcp55/early_smbus.c index a849eba..f52d079 100644 --- a/src/southbridge/nvidia/mcp55/early_smbus.c +++ b/src/southbridge/nvidia/mcp55/early_smbus.c @@ -19,6 +19,7 @@
#include <arch/io.h> #include <console/console.h> +#include <device/pci.h> #include "smbus.h" #include "mcp55.h"
-
Arthur Heymans (Code Review) -
Kyösti Mälkki (Code Review)