[XS] Change in coreboot[main]: soc/intel/alderlake: Configure DDR5 Physical channel width to 64

[Paul Menzel (Code Review)]

Attention is currently required from: Arthur Heymans, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Tarun.

Paul Menzel has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/84085?usp=email )

The change is no longer submittable: All-Comments-Resolved is unsatisfied now.

Change subject: soc/intel/alderlake: Configure DDR5 Physical channel width to 64
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Patch Set 1: Code-Review+1

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/84085/comment/f940e385_8ed1f249?usp... :
PS1, Line 7: alderlake
meteorlake

https://review.coreboot.org/c/coreboot/+/84085/comment/fb888a69_450c781a?usp... :
PS1, Line 15: bufferoverflow
buffer overflow