[S] Change in coreboot[main]: sb/intel/bd82x6x: Honor POST code Kconfig option

[Felix Singer (Code Review)]

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79725?usp=email )

Change subject: sb/intel/bd82x6x: Honor POST code Kconfig option
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sb/intel/bd82x6x: Honor POST code Kconfig option

This southbridge can route POST codes written to port 0x80 to either
LPC or PCI, but currently always route them to LPC. Change it so that
POST codes are routed to PCI if CONFIG(POST_DEVICE_PCI_PCIE) is
selected, LPC otherwise.

Rename the static function because POST codes no longer always go to
LPC.

Change-Id: I455d7aff27154d6821e262a21248e8c7306e2d61
Signed-off-by: Keith Hui 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79725
Tested-by: build bot (Jenkins) 
Reviewed-by: Felix Singer 
Reviewed-by: Nico Huber 
---
M src/southbridge/intel/bd82x6x/bootblock.c
1 file changed, 7 insertions(+), 4 deletions(-)

Approvals:
  Nico Huber: Looks good to me, but someone else must approve
  Felix Singer: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c
index a3228e7..3260021 100644
--- a/src/southbridge/intel/bd82x6x/bootblock.c
+++ b/src/southbridge/intel/bd82x6x/bootblock.c
@@ -5,10 +5,13 @@
 #include <southbridge/intel/common/early_spi.h>
 #include "pch.h"

-static void enable_port80_on_lpc(void)
+static void setup_port80(void)
 {
-	/* Enable port 80 POST on LPC */
-	RCBA32(GCS) &= (~0x04);
+	/* Enable port 80 POST */
+	if (CONFIG(POST_DEVICE_PCI_PCIE))
+		RCBA32(GCS) |= 0x04; /* ... on PCI(e) */
+	else
+		RCBA32(GCS) &= (~0x04); /* ... on LPC */
 }

static void set_spi_speed(void)
@@ -37,7 +40,7 @@

early_pch_init();

-	enable_port80_on_lpc();
+	setup_port80();
    set_spi_speed();

/* Enable upper 128bytes of CMOS */