Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58387 )
Change subject: cpu/x86/lapic: Move LAPIC configuration to MP init ......................................................................
cpu/x86/lapic: Move LAPIC configuration to MP init
Implementation for setup_lapic() did two things -- call enable_lapic() and virtual_wire_mode_init().
In PARALLEL_MP case enable_lapic() was redundant as it was already executed prior to initialize_cpu() call. For the !PARALLEL_MP case enable_lapic() is added to AP CPUs.
Change-Id: I5caf94315776a499e9cf8f007251b61f51292dc5 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/58387 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/amd/agesa/family14/model_14_init.c M src/cpu/amd/agesa/family15tn/model_15_init.c M src/cpu/amd/agesa/family16kb/model_16_init.c M src/cpu/amd/pi/00730F01/model_16_init.c M src/cpu/intel/common/common_init.c M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_1067x/model_1067x_init.c M src/cpu/intel/model_106cx/model_106cx_init.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/cpu/intel/model_65x/model_65x_init.c M src/cpu/intel/model_67x/model_67x_init.c M src/cpu/intel/model_68x/model_68x_init.c M src/cpu/intel/model_6bx/model_6bx_init.c M src/cpu/intel/model_6ex/model_6ex_init.c M src/cpu/intel/model_6fx/model_6fx_init.c M src/cpu/intel/model_6xx/model_6xx_init.c M src/cpu/intel/model_f2x/model_f2x_init.c M src/cpu/intel/model_f3x/model_f3x_init.c M src/cpu/intel/model_f4x/model_f4x_init.c M src/cpu/qemu-x86/qemu.c M src/cpu/x86/lapic/lapic.c M src/cpu/x86/lapic/lapic_cpu_init.c M src/cpu/x86/mp_init.c M src/include/cpu/x86/lapic.h M src/soc/amd/cezanne/cpu.c M src/soc/amd/picasso/cpu.c M src/soc/amd/sabrina/cpu.c M src/soc/amd/stoneyridge/cpu.c M src/soc/intel/alderlake/cpu.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/baytrail/cpu.c M src/soc/intel/braswell/cpu.c M src/soc/intel/cannonlake/cpu.c M src/soc/intel/denverton_ns/cpu.c M src/soc/intel/elkhartlake/cpu.c M src/soc/intel/icelake/cpu.c M src/soc/intel/jasperlake/cpu.c M src/soc/intel/skylake/cpu.c M src/soc/intel/tigerlake/cpu.c M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/cpx/cpu.c 42 files changed, 12 insertions(+), 143 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 4cf0f45..8b67a95 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -7,7 +7,6 @@ #include <cpu/amd/mtrr.h> #include <device/device.h> #include <cpu/x86/pae.h> -#include <cpu/x86/lapic.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> #include <acpi/acpi.h> @@ -57,9 +56,6 @@ /* zero the machine check error status registers */ mca_clear_status();
- /* Enable the local CPU APICs */ - setup_lapic(); - #if CONFIG(LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff;
diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index d13fb9b..77f9e9a 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -8,7 +8,6 @@ #include <cpu/x86/smm.h> #include <device/device.h> #include <cpu/x86/pae.h> -#include <cpu/x86/lapic.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> #include <acpi/acpi.h> @@ -59,9 +58,6 @@ /* zero the machine check error status registers */ mca_clear_status();
- /* Enable the local CPU APICs */ - setup_lapic(); - #if CONFIG(LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff;
diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c index 2915565..2ced7b9 100644 --- a/src/cpu/amd/agesa/family16kb/model_16_init.c +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -7,7 +7,6 @@ #include <cpu/amd/mtrr.h> #include <device/device.h> #include <cpu/x86/pae.h> -#include <cpu/x86/lapic.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> #include <acpi/acpi.h> @@ -57,9 +56,6 @@ /* zero the machine check error status registers */ mca_clear_status();
- /* Enable the local CPU APICs */ - setup_lapic(); - #if CONFIG(LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff;
diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index f84b03a..c743ffe 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -11,7 +11,6 @@ #include <device/device.h> #include <device/pci.h> #include <cpu/x86/pae.h> -#include <cpu/x86/lapic.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> #include <smp/node.h> @@ -26,9 +25,6 @@ /* zero the machine check error status registers */ mca_clear_status();
- /* Enable the local CPU APICs */ - setup_lapic(); - if (CONFIG(LOGICAL_CPUS)) { siblings = cpuid_ecx(0x80000008) & 0xff;
diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index 0f40e4b..24e3eeb 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -4,7 +4,6 @@ #include <arch/cpu.h> #include <console/console.h> #include <cpu/intel/msr.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/msr.h> #include "common.h"
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index d4f3587..90ac5f4 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -7,7 +7,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/mp.h> -#include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/intel/smm_reloc.h> #include <cpu/intel/speedstep.h> @@ -541,9 +540,7 @@ /* Clear out pending MCEs */ configure_mca();
- /* Enable the local CPU APICs */ enable_lapic_tpr(); - setup_lapic();
/* Set virtualization based on Kconfig option */ set_vmx_and_lock(); diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 33187d7..02e6032 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -4,7 +4,6 @@ #include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/msr.h> -#include <cpu/x86/lapic.h> #include <cpu/intel/speedstep.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -256,9 +255,6 @@ fill_processor_name(processor_name); printk(BIOS_INFO, "CPU: %s.\n", processor_name);
- /* Enable the local CPU APICs */ - setup_lapic(); - /* Configure C States */ configure_c_states(quad);
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 278d8de..4cf16d8 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -4,7 +4,6 @@ #include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/msr.h> -#include <cpu/x86/lapic.h> #include <cpu/intel/speedstep.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -67,9 +66,6 @@ fill_processor_name(processor_name); printk(BIOS_INFO, "CPU: %s.\n", processor_name);
- /* Enable the local CPU APICs */ - setup_lapic(); - /* Configure C States */ configure_c_states();
diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index e77f9aa..35b153e 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -91,9 +91,7 @@ /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT
- /* Enable the local CPU APICs */ enable_lapic_tpr(); - setup_lapic();
/* Set virtualization based on Kconfig option */ set_vmx_and_lock(); diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 9de6b38..52d11d7 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -7,7 +7,6 @@ #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> @@ -338,9 +337,7 @@ /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT
- /* Enable the local CPU APICs */ enable_lapic_tpr(); - setup_lapic();
/* Set virtualization based on Kconfig option */ set_vmx_and_lock(); diff --git a/src/cpu/intel/model_65x/model_65x_init.c b/src/cpu/intel/model_65x/model_65x_init.c index 9a17f70..15246b6 100644 --- a/src/cpu/intel/model_65x/model_65x_init.c +++ b/src/cpu/intel/model_65x/model_65x_init.c @@ -3,7 +3,6 @@ #include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> #include <cpu/intel/l2_cache.h> @@ -19,9 +18,6 @@ enable_cache(); x86_setup_mtrrs(); x86_mtrr_check(); - - /* Enable the local CPU APICs */ - setup_lapic(); };
static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_67x/model_67x_init.c b/src/cpu/intel/model_67x/model_67x_init.c index 6a2689d..d524705 100644 --- a/src/cpu/intel/model_67x/model_67x_init.c +++ b/src/cpu/intel/model_67x/model_67x_init.c @@ -3,7 +3,6 @@ #include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> #include <cpu/intel/l2_cache.h> @@ -22,9 +21,6 @@ /* Setup MTRRs */ x86_setup_mtrrs(); x86_mtrr_check(); - - /* Enable the local CPU APICs */ - setup_lapic(); }
static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_68x/model_68x_init.c b/src/cpu/intel/model_68x/model_68x_init.c index 2344cb7..0b5d454 100644 --- a/src/cpu/intel/model_68x/model_68x_init.c +++ b/src/cpu/intel/model_68x/model_68x_init.c @@ -4,7 +4,6 @@ #include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -26,9 +25,6 @@ /* Setup MTRRs */ x86_setup_mtrrs(); x86_mtrr_check(); - - /* Enable the local CPU APICs */ - setup_lapic(); }
static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_6bx/model_6bx_init.c b/src/cpu/intel/model_6bx/model_6bx_init.c index f27a63a..0e54f93 100644 --- a/src/cpu/intel/model_6bx/model_6bx_init.c +++ b/src/cpu/intel/model_6bx/model_6bx_init.c @@ -4,7 +4,6 @@ #include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -26,9 +25,6 @@ /* Setup MTRRs */ x86_setup_mtrrs(); x86_mtrr_check(); - - /* Enable the local CPU APICs */ - setup_lapic(); }
static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 34646ad..bfa4a3e 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -4,7 +4,6 @@ #include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/msr.h> -#include <cpu/x86/lapic.h> #include <cpu/intel/speedstep.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -106,9 +105,6 @@ /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT
- /* Enable the local CPU APICs */ - setup_lapic(); - /* Configure C States */ configure_c_states();
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 72ece23..a481a67 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -4,7 +4,6 @@ #include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/msr.h> -#include <cpu/x86/lapic.h> #include <cpu/intel/speedstep.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -120,9 +119,6 @@ /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT
- /* Enable the local CPU APICs */ - setup_lapic(); - /* Configure C States */ configure_c_states();
diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c index 48a045e..f9afc6c 100644 --- a/src/cpu/intel/model_6xx/model_6xx_init.c +++ b/src/cpu/intel/model_6xx/model_6xx_init.c @@ -3,7 +3,6 @@ #include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h>
@@ -16,9 +15,6 @@
/* Update the microcode */ intel_update_microcode_from_cbfs(); - - /* Enable the local CPU APICs */ - setup_lapic(); };
static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c index 9f365c6..294d579 100644 --- a/src/cpu/intel/model_f2x/model_f2x_init.c +++ b/src/cpu/intel/model_f2x/model_f2x_init.c @@ -3,7 +3,6 @@ #include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/intel/hyperthreading.h> #include <cpu/intel/common/common.h> @@ -23,9 +22,6 @@ intel_update_microcode_from_cbfs(); }
- /* Enable the local CPU APICs */ - setup_lapic(); - /* Start up my CPU siblings */ intel_sibling_init(cpu); }; diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index ba3a4d6..fdc5a1e 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -3,7 +3,6 @@ #include <device/device.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/intel/hyperthreading.h> #include <cpu/intel/common/common.h> @@ -23,9 +22,6 @@ intel_update_microcode_from_cbfs(); }
- /* Enable the local CPU APICs */ - setup_lapic(); - /* Start up my CPU siblings */ if (!CONFIG(PARALLEL_MP)) intel_sibling_init(cpu); diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c index ee6761e..b495dee 100644 --- a/src/cpu/intel/model_f4x/model_f4x_init.c +++ b/src/cpu/intel/model_f4x/model_f4x_init.c @@ -2,16 +2,12 @@
#include <device/device.h> #include <cpu/cpu.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/cache.h>
static void model_f4x_init(struct device *cpu) { /* Turn on caching if we haven't already */ enable_cache(); - - /* Enable the local CPU APICs */ - setup_lapic(); };
static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/qemu-x86/qemu.c b/src/cpu/qemu-x86/qemu.c index 9f01007..f0cdb58 100644 --- a/src/cpu/qemu-x86/qemu.c +++ b/src/cpu/qemu-x86/qemu.c @@ -2,11 +2,9 @@
#include <cpu/cpu.h> #include <device/device.h> -#include <cpu/x86/lapic.h>
static void qemu_cpu_init(struct device *dev) { - setup_lapic(); }
static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c index 9003534..76f2d89 100644 --- a/src/cpu/x86/lapic/lapic.c +++ b/src/cpu/x86/lapic/lapic.c @@ -65,13 +65,7 @@ return LAPIC_DEFAULT_BASE; }
-/* See if I need to initialize the local APIC */ -static int need_lapic_init(void) -{ - return CONFIG(SMP) || CONFIG(IOAPIC); -} - -static void lapic_virtual_wire_mode_init(void) +void setup_lapic_interrupts(void) { /* * Set Task Priority to 'accept all'. @@ -94,17 +88,3 @@
lapic_update32(LAPIC_LVT1, ~mask, LAPIC_DELIVERY_MODE_NMI); } - -void setup_lapic(void) -{ - /* Enable the local APIC */ - if (need_lapic_init()) - enable_lapic(); - else if (!CONFIG(UDELAY_LAPIC)) - disable_lapic(); - - /* This programming is for PIC mode i8259 interrupts to be delivered to CPU - while LAPIC is enabled. */ - if (need_lapic_init()) - lapic_virtual_wire_mode_init(); -} diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 7780be2..837d32f 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -298,6 +298,11 @@ cr4_val |= (CR4_OSFXSR | CR4_OSXMMEXCPT); write_cr4(cr4_val); #endif + + /* Ensure the local APIC is enabled */ + enable_lapic(); + setup_lapic_interrupts(); + cpu_initialize(index);
spin_unlock(&start_cpu_lock); @@ -376,8 +381,10 @@ info = cpu_info();
/* Ensure the local APIC is enabled */ - if (is_smp_boot()) + if (is_smp_boot()) { enable_lapic(); + setup_lapic_interrupts(); + }
/* Get the device path of the boot CPU */ cpu_path.type = DEVICE_PATH_APIC; diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index abe903c..fee5940 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -185,6 +185,7 @@
/* Ensure the local APIC is enabled */ enable_lapic(); + setup_lapic_interrupts();
info->cpu = cpus_dev[info->index];
@@ -543,6 +544,7 @@
/* Ensure the local APIC is enabled */ enable_lapic(); + setup_lapic_interrupts();
/* Set the device path of the boot CPU. */ cpu_path.type = DEVICE_PATH_APIC; diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index e131d2e..7006dbc 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -177,6 +177,6 @@
void enable_lapic(void); void disable_lapic(void); -void setup_lapic(void); +void setup_lapic_interrupts(void);
#endif /* CPU_X86_LAPIC_H */ diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c index 440b5ba..adc99d0 100644 --- a/src/soc/amd/cezanne/cpu.c +++ b/src/soc/amd/cezanne/cpu.c @@ -8,7 +8,6 @@ #include <console/console.h> #include <cpu/amd/microcode.h> #include <cpu/cpu.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> @@ -62,7 +61,6 @@ static void zen_2_3_init(struct device *dev) { check_mca(); - setup_lapic(); set_cstate_io_addr();
amd_update_microcode_from_cbfs(); diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index b80b0f7..de6e9c0 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -10,7 +10,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/smm.h> -#include <cpu/x86/lapic.h> #include <device/device.h> #include <device/pci_ops.h> #include <soc/pci_devs.h> @@ -66,7 +65,6 @@ static void model_17_init(struct device *dev) { check_mca(); - setup_lapic(); set_cstate_io_addr();
amd_update_microcode_from_cbfs(); diff --git a/src/soc/amd/sabrina/cpu.c b/src/soc/amd/sabrina/cpu.c index 0aa487c..c355a70 100644 --- a/src/soc/amd/sabrina/cpu.c +++ b/src/soc/amd/sabrina/cpu.c @@ -10,7 +10,6 @@ #include <console/console.h> #include <cpu/amd/microcode.h> #include <cpu/cpu.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> @@ -64,7 +63,6 @@ static void zen_2_3_init(struct device *dev) { check_mca(); - setup_lapic(); set_cstate_io_addr();
amd_update_microcode_from_cbfs(); diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 6be76bf..3cd3a95 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -9,7 +9,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/smm.h> -#include <cpu/x86/lapic.h> #include <device/device.h> #include <device/pci_ops.h> #include <soc/pci_devs.h> @@ -65,7 +64,6 @@ static void model_15_init(struct device *dev) { check_mca(); - setup_lapic();
/* * Per AMD, sync an undocumented MSR with the PSP base address. diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 3b3a7a2..426f621 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -9,7 +9,6 @@ #include <console/console.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <cpu/intel/smm_reloc.h> @@ -110,9 +109,7 @@ * every bank. */ mca_configure();
- /* Enable the local CPU apics */ enable_lapic_tpr(); - setup_lapic();
/* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 74aeee9..e892017 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -5,7 +5,6 @@ #include <console/console.h> #include "chip.h" #include <cpu/cpu.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/intel/microcode.h> #include <cpu/intel/turbo.h> @@ -154,8 +153,6 @@ x86_setup_mtrrs_with_detect(); x86_mtrr_check();
- /* Enable the local CPU apics */ - setup_lapic(); }
#if !CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index eb24f7b..1dbc3d7 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -36,9 +36,6 @@ { printk(BIOS_DEBUG, "Init BayTrail core.\n");
- /* Enable the local CPU apics */ - setup_lapic(); - /* * The turbo disable bit is actually scoped at building block level -- not package. * For non-BSP cores that are within a building block, enable turbo. The cores within diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 7c7a15d..b11007d 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -36,9 +36,6 @@ { printk(BIOS_DEBUG, "Init Braswell core.\n");
- /* Enable the local cpu apics */ - setup_lapic(); - /* * The turbo disable bit is actually scoped at building block level -- not package. * For non-BSP cores that are within a building block, enable turbo. The cores within diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 10921a2..b7ca2b4 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -2,7 +2,6 @@
#include <console/console.h> #include <device/pci.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <cpu/intel/smm_reloc.h> @@ -118,9 +117,7 @@ * every bank. */ mca_configure();
- /* Enable the local CPU apics */ enable_lapic_tpr(); - setup_lapic();
/* Configure c-state interrupt response time */ configure_c_states(cfg); diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index 3747a48..93657fe 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -100,9 +100,6 @@ /* Enable Turbo */ enable_turbo();
- /* Enable the local CPU apics */ - setup_lapic(); - /* Enable speed step. Always ON.*/ msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= SPEED_STEP_ENABLE_BIT; diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c index 0cc3935..3e0dae1 100644 --- a/src/soc/intel/elkhartlake/cpu.c +++ b/src/soc/intel/elkhartlake/cpu.c @@ -3,7 +3,6 @@ #include <cpu/intel/smm_reloc.h> #include <cpu/intel/turbo.h> #include <cpu/intel/common/common.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <device/pci.h> @@ -70,9 +69,7 @@ * every bank. */ mca_configure();
- /* Enable the local CPU apics */ enable_lapic_tpr(); - setup_lapic();
/* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index 37978ea..f503fcd 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <device/pci.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <cpu/intel/smm_reloc.h> @@ -103,9 +102,7 @@ * every bank. */ mca_configure();
- /* Enable the local CPU apics */ enable_lapic_tpr(); - setup_lapic();
/* Configure c-state interrupt response time */ configure_c_states(); diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c index af39c94..01cd6ac 100644 --- a/src/soc/intel/jasperlake/cpu.c +++ b/src/soc/intel/jasperlake/cpu.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <device/pci.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <cpu/intel/smm_reloc.h> @@ -70,9 +69,7 @@ * every bank. */ mca_configure();
- /* Enable the local CPU apics */ enable_lapic_tpr(); - setup_lapic();
/* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 63a0466..3439836 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -5,7 +5,6 @@ #include <device/pci.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/intel/common/common.h> #include <cpu/intel/microcode.h> @@ -118,9 +117,7 @@ * every bank. */ mca_configure();
- /* Enable the local CPU apics */ enable_lapic_tpr(); - setup_lapic();
/* Configure c-state interrupt response time */ configure_c_states(); diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index d225c50..ffccdcc 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -7,7 +7,6 @@ */
#include <device/pci.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <cpu/intel/smm_reloc.h> @@ -76,9 +75,7 @@ * every bank. */ mca_configure();
- /* Enable the local CPU apics */ enable_lapic_tpr(); - setup_lapic();
/* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index a4da344..41dde0d 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -3,7 +3,6 @@ #include <arch/ioapic.h> #include <console/console.h> #include <console/debug.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -181,7 +180,6 @@ override_hpet_ioapic_bdf(); pch_enable_ioapic(); pch_lock_dmictl(); - setup_lapic(); p2sb_unhide(); }
diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index 07c2db7..0951ae3 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -11,7 +11,6 @@ #include <cpu/intel/microcode.h> #include <cpu/intel/smm_reloc.h> #include <cpu/intel/turbo.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/mtrr.h> #include <intelblocks/cpulib.h> @@ -78,7 +77,6 @@
printk(BIOS_SPEW, "%s dev: %s, cpu: %d, apic_id: 0x%x\n", __func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id); - setup_lapic();
/* * Set HWP base feature, EPP reg enumeration, lock thermal and msr
-
Kyösti Mälkki (Code Review)