Jason Glenesk has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52603 )
Change subject: vc/amd/fsp/cezanne:Add s0i_enable upd control ......................................................................
vc/amd/fsp/cezanne:Add s0i_enable upd control
Add upd to enable S0i3 in fsp.
BUG=178728116
Change-Id: I01759caa4d72e284b2b960634f89c6a2ab1dad57 Signed-off-by: Jason Glenesk jason.glenesk@amd.corp-partner.google.com --- M src/vendorcode/amd/fsp/cezanne/FspmUpd.h 1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/52603/1
diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h index 66c8ab8..dd59d52 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h +++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h @@ -100,7 +100,8 @@ /** Offset 0x04A4**/ uint8_t fch_ioapic_id; /** Offset 0x04A5**/ uint8_t sata_enable; /** Offset 0x04A6**/ uint8_t fch_reserved[32]; - /** Offset 0x04C6**/ uint8_t UnusedUpdSpace0[58]; + /** Offset 0x04A7**/ uint8_t s0i3_enable; + /** Offset 0x04C6**/ uint8_t UnusedUpdSpace0[57]; /** Offset 0x0500**/ uint16_t UpdTerminator; } FSP_M_CONFIG;