Attention is currently required from: Anil Kumar K, Bora Guvendik, Felix Held, Hannah Williams, Jamie Ryu.
Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email )
Change subject: soc/intel/common/block/pmc: Add GPE1 functions ......................................................................
Patch Set 11:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/pmclib.h:
https://review.coreboot.org/c/coreboot/+/84104/comment/c56cbf85_0423e45c?usp... : PS11, Line 241: gpe0_mask
Adding GPE1 ref from PTL EDS links for internal device events:
PME_B0 events: https://edc.intel.com/preview/content/www/us/en/secure/design/confidential/p...
hot plug events: https://edc.intel.com/preview/content/www/us/en/secure/design/confidential/p...
PCIe events: https://edc.intel.com/preview/content/www/us/en/secure/design/confidential/p...
@cliff, the question here is what if one design wish to use GPE1, will they have to pass the GPE0 register details to know if the corresponding GPE1 bit is set or not ? My understanding is if GPE1 is being used, we will publish a new sets of GPE events specific for GPE1 and in such case, we will read GPE1 status/en bit and not necessarily try to map GPE0 events against GPE1 events.
if GPE1 is not there, then we use GPE0 and PMC_B0 event muxed for many other internal IPs as well and not as specific as GPE1 bit definition that i have shared.