[L] Change in coreboot[master]: mb/google/skyrim: Add named GPIO's - coreboot-gerrit

20 Apr 2023

Attention is currently required from: Jason Nien, Martin Roth.
Jon Murphy has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74592 )
Change subject: mb/google/skyrim: Add named GPIO's
......................................................................
mb/google/skyrim: Add named GPIO's
Add named GPIO's to help prevent confusion in GPIO management
BUG=b:278968729
TEST=builds
Change-Id: If907478442ea7acb80b2e413926d173d188ce340
Signed-off-by: Jon Murphy jpmurphy@google.com
---
M src/mainboard/google/skyrim/chromeos.c
M src/mainboard/google/skyrim/ec.c
M src/mainboard/google/skyrim/port_descriptors.c
M src/mainboard/google/skyrim/variants/baseboard/gpio.c
M src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h
M src/mainboard/google/skyrim/variants/baseboard/include/baseboard/gpio.h
M src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/skyrim/variants/baseboard/smihandler.c
M src/mainboard/google/skyrim/variants/baseboard/tpm_tis.c
A src/mainboard/google/skyrim/variants/crystaldrift/include/variant/gpio.h
M src/mainboard/google/skyrim/variants/frostflow/gpio.c
A src/mainboard/google/skyrim/variants/frostflow/include/variant/gpio.h
M src/mainboard/google/skyrim/variants/markarth/gpio.c
A src/mainboard/google/skyrim/variants/markarth/include/variant/gpio.h
M src/mainboard/google/skyrim/variants/markarth/port_descriptors.c
A src/mainboard/google/skyrim/variants/skyrim/include/variant/gpio.h
M src/mainboard/google/skyrim/variants/winterhold/gpio.c
A src/mainboard/google/skyrim/variants/winterhold/include/variant/gpio.h
M src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c
M src/mainboard/google/skyrim/verstage.c
20 files changed, 229 insertions(+), 219 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/74592/1

diff --git a/src/mainboard/google/skyrim/chromeos.c b/src/mainboard/google/skyrim/chromeos.c
index c65e045..d020c09 100644
--- a/src/mainboard/google/skyrim/chromeos.c
+++ b/src/mainboard/google/skyrim/chromeos.c
@@ -1,9 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
-#include <baseboard/gpio.h>
 #include <boot/coreboot_tables.h>
 #include <bootmode.h>
-#include <gpio.h>
+#include <variant/gpio.h>
 #include <vendorcode/google/chromeos/chromeos.h>
void fill_lb_gpios(struct lb_gpios *gpios)
diff --git a/src/mainboard/google/skyrim/ec.c b/src/mainboard/google/skyrim/ec.c
index f265cbf..82d3ba9 100644
--- a/src/mainboard/google/skyrim/ec.c
+++ b/src/mainboard/google/skyrim/ec.c
@@ -4,9 +4,9 @@
 #include <amdblocks/smi.h>
 #include <console/console.h>
 #include <ec/google/chromeec/ec.h>
-#include <gpio.h>
 #include <soc/smi.h>
 #include <variant/ec.h>
+#include <variant/gpio.h>
static const struct sci_source espi_sci_sources[] = {
    {
diff --git a/src/mainboard/google/skyrim/port_descriptors.c b/src/mainboard/google/skyrim/port_descriptors.c
index 80839a0..2e18d84 100644
--- a/src/mainboard/google/skyrim/port_descriptors.c
+++ b/src/mainboard/google/skyrim/port_descriptors.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
+#include <variant/gpio.h>
 #include <baseboard/variants.h>
-#include <gpio.h>
 #include <soc/platform_descriptors.h>
 #include <types.h>
@@ -35,7 +35,7 @@
    	.link_hotplug = 3,
    	.link_aspm = ASPM_L1,
    	.link_aspm_L1_1 = true,
-		.gpio_group_id = GPIO_27,
+		.gpio_group_id = SSD_AUX_RST_L,
    	.clk_req = CLK_REQ1,
    },
    { /* SSD */
@@ -50,7 +50,7 @@
    	.link_aspm = ASPM_L1,
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
-		.gpio_group_id = GPIO_6,
+		.gpio_group_id = SSD_AUX_RST_L,
    	.clk_req = CLK_REQ0,
    },
 };
diff --git a/src/mainboard/google/skyrim/variants/baseboard/gpio.c b/src/mainboard/google/skyrim/variants/baseboard/gpio.c
index 969a995..bf80de4 100644
--- a/src/mainboard/google/skyrim/variants/baseboard/gpio.c
+++ b/src/mainboard/google/skyrim/variants/baseboard/gpio.c
@@ -1,208 +1,119 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
-#include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
-#include <gpio.h>
+#include <variant/gpio.h>
/* GPIO configuration in ramstage*/
 static const struct soc_amd_gpio base_gpio_table[] = {
-	/* PWR_BTN_L */
-	PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE),
-	/* SYS_RESET_L */
-	PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE),
-	/* WAKE_L */
-	PAD_NF_SCI(GPIO_2, WAKE_L, PULL_NONE, EDGE_LOW),
-	/* SOC_PEN_DETECT_ODL */
-	PAD_WAKE(GPIO_3, PULL_NONE, EDGE_LOW, S0i3),
-	/* EN_PWR_FP */
-	PAD_GPO(GPIO_4, LOW),
-	/* EN_PP3300_TCHPAD */
-	PAD_GPO(GPIO_5, HIGH),
-	/* SSD_AUX_RESET_L */
-	PAD_GPO(GPIO_6, HIGH),
-	/* WLAN_AUX_RST_L */
-	PAD_GPO(GPIO_7, HIGH),
-	/* EN_PWR_WWAN_X */
-	PAD_GPO(GPIO_8, LOW),
-	/* EN_PP3300_WLAN */
-	PAD_GPO(GPIO_9, HIGH),
-	/* BT_DISABLE */
-	PAD_GPO(GPIO_10, LOW),
-	/* EC_SOC_WAKE_ODL */
-	PAD_SCI(GPIO_11, PULL_NONE, EDGE_LOW),
-	/* SOC_FP_RST_L */
-	PAD_GPO(GPIO_12, LOW),
-	/* GPIO_13 - GPIO_15: Not available */
-	/* USB_OC0_L */
-	PAD_NF(GPIO_16, USB_OC0_L, PULL_NONE),
-	/* SOC_SAR_INT_L */
-	PAD_SCI(GPIO_17, PULL_NONE, EDGE_LOW),
-	/* GSC_SOC_INT_L */
-	PAD_INT(GPIO_18, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
-	/* I2C3_SCL */
-	PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE),
-	/* I2C3_SDA */
-	PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE),
-	/* WLAN_DISABLE */
-	PAD_GPO(GPIO_21, LOW),
-	/* ESPI_ALERT_L */
-	PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE),
-	/* AC_PRES */
-	PAD_NF(GPIO_23, AC_PRES, PULL_UP),
-	/* SOC_FP_INT_L */
-	PAD_SCI(GPIO_24, PULL_NONE, LEVEL_LOW),
-	/* GPIO_25: Not available */
-	/* PCIE_RST0_L */
-	PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH),
-	/* SD_AUX_RESET_L  */
-	PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH),
-	/* GPIO_28: Not available */
-	/* TCHSCR_INT_ODL */
-	PAD_GPI(GPIO_29, PULL_NONE),
-	/* ESPI_CS_L */
-	PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE),
-	/* Unused */
+	PAD_NF(SOC_PWR_BTN_L, PWR_BTN_L, PULL_NONE),
+	PAD_NF(SYS_RST_ODL, SYS_RESET_L, PULL_NONE),
+	PAD_NF_SCI(SOC_PCIE_WAKE_L, WAKE_L, PULL_NONE, EDGE_LOW),
+	PAD_WAKE(SOC_PEN_DETECT_ODL, PULL_NONE, EDGE_LOW, S0i3),
+	PAD_GPO(EN_PWR_FP, LOW),
+	PAD_GPO(EN_PP3300_TCHPAD, HIGH),
+	PAD_GPO(SSD_AUX_RST_L, HIGH),
+	PAD_GPO(WLAN_AUX_RST_L, HIGH),
+	PAD_GPO(EN_PWR_WWAN_X, LOW),
+	PAD_GPO(EN_PP3300_WLAN, HIGH),
+	PAD_GPO(BT_DISABLE, LOW),
+	PAD_SCI(EC_SOC_WAKE_ODL, PULL_NONE, EDGE_LOW),
+	PAD_GPO(SOC_FP_RST_L, LOW),
+	PAD_NF(USB_FAULT_R_ODL, USB_OC0_L, PULL_NONE),
+	PAD_SCI(SOC_SAR_INT_R_L, PULL_NONE, EDGE_LOW),
+	PAD_INT(GSC_SOC_INT_L, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
+	PAD_NF(SOC_I2C_3_SCL, I2C3_SCL, PULL_NONE),
+	PAD_NF(SOC_I2C_3_SDA, I2C3_SDA, PULL_NONE),
+	PAD_GPO(WLAN_DISABLE, LOW),
+	PAD_NF(ESPI_EC_ALERT_SOC_R_ODL, ESPI_ALERT_D1, PULL_NONE),
+	PAD_NF(SOC_AC_PRES, AC_PRES, PULL_UP),
+	PAD_SCI(SOC_FP_INT_L, PULL_NONE, LEVEL_LOW),
+	PAD_NFO(SOC_PCIE_RST0_R_L, PCIE_RST0_L, HIGH),
+	PAD_NFO(SD_AUX_RST_SOC_L, PCIE_RST1_L, HIGH),
+	PAD_GPI(TCHSCR_INT_ODL, PULL_NONE),
+	PAD_NF(ESPI_SOC_CS_EC_R_L, ESPI_CS_L, PULL_NONE),
+	/* GPIO_31 Unused */
    PAD_NC(GPIO_31),
-	/* LPC_RST_L */
-	PAD_NF(GPIO_32, LPC_RST_L, PULL_NONE),
-	/* GPIO_33 - GPIO_39: Not available */
-	/* SOC_TCHPAD_INT_ODL */
-	PAD_SCI(GPIO_40, PULL_NONE, LEVEL_LOW),
-	/* GPIO_41: Not available */
-	/* WWAN_RST_L */
-	PAD_GPO(GPIO_42, HIGH),
-	/* GPIO_43 - GPIO_66: Not available */
-	/* GPIO_67 (Unused) */
+	PAD_NF(LPC_RST_L_MB, LPC_RST_L, PULL_NONE),
+	PAD_SCI(SOC_TCHPAD_INT_ODL, PULL_NONE, LEVEL_LOW),
+	PAD_GPO(WWAN_RST, HIGH),
+	/* GPIO_67 Unused */
    PAD_NC(GPIO_67),
-	/* ESPI1_DATA2 */
-	PAD_NF(GPIO_68, SPI1_DAT2, PULL_NONE),
-	/* ESPI1_DATA3 */
-	PAD_NF(GPIO_69, SPI1_DAT3, PULL_NONE),
-	/* SOC_DISABLE_DISP_BL */
-	PAD_GPO(GPIO_74, LOW),
-	/* TCHSCR_REPORT_EN */
-	PAD_GPO(GPIO_76, LOW),
-	/* ESPI_CLK */
-	PAD_NF(GPIO_77, SPI1_CLK, PULL_NONE),
-	/* EN_PP3300_CAM */
-	PAD_GPO(GPIO_78, HIGH),
-	/* ESPI1_DATA1 */
-	PAD_NF(GPIO_80, SPI1_DAT1, PULL_NONE),
-	/* ESPI1_DATA0 */
-	PAD_NF(GPIO_81, SPI1_DAT0, PULL_NONE),
-	/* EC_SOC_INT_ODL */
-	PAD_GPI(GPIO_84, PULL_NONE),
-	/* RAM_ID_1 / DEV_BEEP_DATA */
-	PAD_GPI(GPIO_85, PULL_NONE),
-	/* RAM_ID_2 / DEV_BEEP_LRCLK */
-	PAD_GPI(GPIO_89, PULL_NONE),
-	/* HP_INT_ODL */
-	PAD_GPI(GPIO_90, PULL_NONE),
-	/* RAM_ID_3 / DEV_BEEP_BCLK */
-	PAD_GPI(GPIO_91, PULL_NONE),
-	/* CLK_REQ0_L / SSD */
-	PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE),
-	/* I2C2_SCL */
-	PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE),
-	/* I2C2_SDA */
-	PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE),
-	/* CLK_REQ1_L / SD */
-	PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE),
-	/* CLK_REQ2_L / WLAN */
-	PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE),
-	/* SOC_FPMCU_BOOT0 */
-	PAD_GPO(GPIO_130, LOW),
-	/* Enable touchscreen, release from reset */
-	/* EN_PP3300_TCHSCR */
-	PAD_GPO(GPIO_131, HIGH),
-	/* TCHSCR_RESET_L */
-	PAD_GPO(GPIO_136, HIGH),
-	/* SOC_BIOS_WP_L */
-	PAD_GPI(GPIO_138, PULL_NONE),
-	/* EN_SPKR */
-	PAD_GPO(GPIO_139, LOW),
-	/* RAM_ID_0 / DEV_BEEP_EN */
-	PAD_GPI(GPIO_144, PULL_NONE),
-	/* UART1_TXD / FP */
-	PAD_NF(GPIO_140, UART1_TXD, PULL_NONE),
-	/* UART0_RXD / DBG */
-	PAD_NF(GPIO_141, UART0_RXD, PULL_NONE),
-	/* UART1_RXD  / FP*/
-	PAD_NF(GPIO_142, UART1_RXD, PULL_NONE),
-	/* UART0_TXD / DBG */
-	PAD_NF(GPIO_143, UART0_TXD, PULL_NONE),
-	/* I2C0_SCL */
-	PAD_NF(GPIO_145, I2C0_SCL, PULL_NONE),
-	/* I2C0_SDA */
-	PAD_NF(GPIO_146, I2C0_SDA, PULL_NONE),
-	/* I2C1_SCL */
-	PAD_NF(GPIO_147, I2C1_SCL, PULL_NONE),
-	/* I2C1_SDA */
-	PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE),
+	PAD_NF(ESPI_SOC_D2_R, SPI1_DAT2, PULL_NONE),
+	PAD_NF(ESPI_SOC_D3_R, SPI1_DAT3, PULL_NONE),
+	PAD_GPO(SOC_DISABLE_DISP_BL_R, LOW),
+	PAD_GPO(TCHSCR_REPORT_EN, LOW),
+	PAD_NF(ESPI_SOC_CLK_R, SPI1_CLK, PULL_NONE),
+	PAD_GPO(EN_PP3300_CAM, HIGH),
+	PAD_NF(ESPI_SOC_D1_R, SPI1_DAT1, PULL_NONE),
+	PAD_NF(ESPI_SOC_D0_R, SPI1_DAT0, PULL_NONE),
+	PAD_GPI(EC_SOC_INT_ODL, PULL_NONE),
+	PAD_GPI(RAM_ID_1, PULL_NONE),
+	PAD_GPI(RAM_ID_2, PULL_NONE),
+	PAD_GPI(HP_INT_ODL, PULL_NONE),
+	PAD_GPI(RAM_ID_3, PULL_NONE),
+	PAD_NF(PCIE_0_SSD_CLKREQ_ODL, CLK_REQ0_L, PULL_NONE),
+	PAD_NF(SOC_I2C_2_SCL, I2C2_SCL, PULL_NONE),
+	PAD_NF(SOC_I2C_2_SDA, I2C2_SDA, PULL_NONE),
+	PAD_NF(PCIE_1_SD_CLKREQ_ODL, CLK_REQ1_L, PULL_NONE),
+	PAD_NF(PCIE_2_WLAN_CLKREQ_ODL, CLK_REQ2_L, PULL_NONE),
+	PAD_GPO(SOC_FPMCU_BOOT0, LOW),
+	PAD_GPO(EN_PP3300_TCHSCR, HIGH),
+	PAD_GPO(TCHSCR_RST_L, HIGH),
+	PAD_GPI(SOC_BIOS_WP_L, PULL_NONE),
+	PAD_GPO(EN_SPKR, LOW),
+	PAD_GPI(RAM_ID_0, PULL_NONE),
+	PAD_NF(UART_SOC_TX_FP_RX, UART1_TXD, PULL_NONE),
+	PAD_NF(UART_DBG_TX_SOC_RX_R, UART0_RXD, PULL_NONE),
+	PAD_NF(UART_FP_TX_SOC_RX, UART1_RXD, PULL_NONE),
+	PAD_NF(UART_SOC_TX_DBG_RX_R, UART0_TXD, PULL_NONE),
+	PAD_NF(SOC_I2C_0_SCL, I2C0_SCL, PULL_NONE),
+	PAD_NF(SOC_I2C_0_SDA, I2C0_SDA, PULL_NONE),
+	PAD_NF(SOC_I2C_1_SCL, I2C1_SCL, PULL_NONE),
+	PAD_NF(SOC_I2C_1_SDA, I2C1_SDA, PULL_NONE),
 };
static const struct soc_amd_gpio espi_gpio_table[] = {
-	/* ESPI_CS_L */
-	PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE),
-	/* ESPI_CLK */
-	PAD_NF(GPIO_77, SPI1_CLK, PULL_NONE),
-	/* ESPI1_DATA0 */
-	PAD_NF(GPIO_81, SPI1_DAT0, PULL_NONE),
-	/* ESPI1_DATA1 */
-	PAD_NF(GPIO_80, SPI1_DAT1, PULL_NONE),
-	/* ESPI1_DATA2 */
-	PAD_NF(GPIO_68, SPI1_DAT2, PULL_NONE),
-	/* ESPI1_DATA3 */
-	PAD_NF(GPIO_69, SPI1_DAT3, PULL_NONE),
-	/* ESPI_ALERT_L */
-	PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE),
+	PAD_NF(ESPI_SOC_CS_EC_R_L, ESPI_CS_L, PULL_NONE),
+	PAD_NF(ESPI_SOC_CLK_R, SPI1_CLK, PULL_NONE),
+	PAD_NF(ESPI_SOC_D0_R, SPI1_DAT0, PULL_NONE),
+	PAD_NF(ESPI_SOC_D1_R, SPI1_DAT1, PULL_NONE),
+	PAD_NF(ESPI_SOC_D2_R, SPI1_DAT2, PULL_NONE),
+	PAD_NF(ESPI_SOC_D3_R, SPI1_DAT3, PULL_NONE),
+	PAD_NF(ESPI_EC_ALERT_SOC_R_ODL, ESPI_ALERT_D1, PULL_NONE),
 };
static const struct soc_amd_gpio tpm_gpio_table[] = {
-	/* I2C3_SCL */
-	PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE),
-	/* I2C3_SDA */
-	PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE),
-	/* GSC_SOC_INT_L */
-	PAD_INT(GPIO_18, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
+	PAD_NF(SOC_I2C_3_SCL, I2C3_SCL, PULL_NONE),
+	PAD_NF(SOC_I2C_3_SDA, I2C3_SDA, PULL_NONE),
+	PAD_INT(GSC_SOC_INT_L, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
 };
/* GPIO configuration in bootblock */
 static const struct soc_amd_gpio bootblock_gpio_table[] = {
    /* Enable WLAN */
-	/* WLAN_DISABLE */
-	PAD_GPO(GPIO_21, LOW),
+	PAD_GPO(WLAN_DISABLE, LOW),
 };
/* Early GPIO configuration */
 static const struct soc_amd_gpio early_gpio_table[] = {
-	/* WLAN_AUX_RESET_L (ACTIVE LOW) */
-	PAD_GPO(GPIO_7, LOW),
+	PAD_GPO(WLAN_AUX_RST_L, LOW),
    /* Power on WLAN */
-	/* EN_PP3300_WLAN */
-	PAD_GPO(GPIO_9, HIGH),
+	PAD_GPO(EN_PP3300_WLAN, HIGH),
 };
/* Romstage GPIO configuration */
 static const struct soc_amd_gpio romstage_gpio_table[] = {
    /* PCIE_RST needs to be brought high before FSP-M runs */
    /* Deassert all AUX_RESET lines & PCIE_RST */
-	/* WLAN_AUX_RESET_L (ACTIVE LOW) */
-	PAD_GPO(GPIO_7, HIGH),
-	/* PCIE_RST0_L */
-	PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH),
-	/* SD_AUX_RESET_L  */
-	PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH),
-	/* SSD_AUX_RESET_L */
-	PAD_GPO(GPIO_6, HIGH),
-	/* CLK_REQ0_L / SSD */
-	PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE),
+	PAD_GPO(WLAN_AUX_RST_L, HIGH),
+	PAD_NFO(SOC_PCIE_RST0_R_L, PCIE_RST0_L, HIGH),
+	PAD_NFO(SD_AUX_RST_SOC_L, PCIE_RST1_L, HIGH),
+	PAD_GPO(SSD_AUX_RST_L, HIGH),
+	PAD_NF(PCIE_0_SSD_CLKREQ_ODL, CLK_REQ0_L, PULL_NONE),
    /* Enable touchscreen, hold in reset */
-	/* EN_PP3300_TCHSCR */
-	PAD_GPO(GPIO_131, HIGH),
-	/* TCHSCR_RESET_L */
-	PAD_GPO(GPIO_136, LOW),
+	PAD_GPO(EN_PP3300_TCHSCR, HIGH),
+	PAD_GPO(TCHSCR_RST_L, LOW),
 };
void baseboard_romstage_gpio_table(const struct soc_amd_gpio **gpio, size_t *size)
diff --git a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h
index c04cc5b..bc2f334 100644
--- a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h
+++ b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h
@@ -5,8 +5,7 @@
#include <ec/ec.h>
 #include <ec/google/chromeec/ec_commands.h>
-#include <baseboard/gpio.h>
-#include <gpio.h>
+#include <variant/gpio.h>
#define MAINBOARD_EC_SCI_EVENTS                                                                \
    (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)                                          \
@@ -73,9 +72,6 @@
 /* Enable EC sync interrupt */
 #define EC_ENABLE_SYNC_IRQ_GPIO
-/* EC sync irq */
-#define EC_SYNC_IRQ GPIO_84
-
 /* Enable EC backed PD MCU device in ACPI */
 #define EC_ENABLE_PD_MCU_DEVICE
diff --git a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/gpio.h
index eb17eff..24244cb 100644
--- a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/gpio.h
+++ b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/gpio.h
@@ -5,7 +5,73 @@
#include <gpio.h>
+#define SOC_PWR_BTN_L GPIO_0
+#define SYS_RST_ODL GPIO_1
+#define SOC_PCIE_WAKE_L GPIO_2
+#define SOC_PEN_DETECT_ODL GPIO_3
+#define EN_PWR_FP GPIO_4
+#define EN_PP3300_TCHPAD GPIO_5
+#define SSD_AUX_RST_L GPIO_6
+#define WLAN_AUX_RST_L GPIO_7
+#define EN_PWR_WWAN_X GPIO_8
+#define EN_PP3300_WLAN GPIO_9
+#define BT_DISABLE GPIO_10
+#define EC_SOC_WAKE_ODL GPIO_11
+#define SOC_FP_RST_L GPIO_12
+#define USB_FAULT_R_ODL GPIO_16
+#define SOC_SAR_INT_R_L GPIO_17
+#define GSC_SOC_INT_L GPIO_18
+#define SOC_I2C_3_SCL GPIO_19
+#define SOC_I2C_3_SDA GPIO_20
+#define WLAN_DISABLE GPIO_21
+#define ESPI_EC_ALERT_SOC_R_ODL GPIO_22
+#define SOC_AC_PRES GPIO_23
+#define SOC_FP_INT_L GPIO_24
+#define SOC_PCIE_RST0_R_L GPIO_26
+#define SD_AUX_RST_SOC_L GPIO_27
+#define TCHSCR_INT_ODL GPIO_29
+#define ESPI_SOC_CS_EC_R_L GPIO_30
+#define LPC_RST_L_MB GPIO_32
+#define SOC_TCHPAD_INT_ODL GPIO_40
+#define WWAN_RST GPIO_42
+#define SOC_TDP_STRAP GPIO_67
+#define ESPI_SOC_D2_R GPIO_68
+#define ESPI_SOC_D3_R GPIO_69
+#define SOC_DISABLE_DISP_BL_R GPIO_74
+#define TCHSCR_REPORT_EN GPIO_76
+#define ESPI_SOC_CLK_R GPIO_77
+#define EN_PP3300_CAM GPIO_78
+#define ESPI_SOC_D1_R GPIO_80
+#define ESPI_SOC_D0_R GPIO_81
+#define EC_SOC_INT_ODL GPIO_84
+#define RAM_ID_1 GPIO_85
+#define RAM_ID_2 GPIO_89
+#define HP_INT_ODL GPIO_90
+#define RAM_ID_3 GPIO_91
+#define PCIE_0_SSD_CLKREQ_ODL GPIO_92
+#define SOC_I2C_2_SCL GPIO_113
+#define SOC_I2C_2_SDA GPIO_114
+#define PCIE_1_SD_CLKREQ_ODL GPIO_115
+#define PCIE_2_WLAN_CLKREQ_ODL GPIO_116
+#define SOC_FPMCU_BOOT0 GPIO_130
+#define EN_PP3300_TCHSCR GPIO_131
+#define TCHSCR_RST_L GPIO_136
+#define SOC_BIOS_WP_L GPIO_138
+#define EN_SPKR GPIO_139
+#define UART_SOC_TX_FP_RX GPIO_140
+#define UART_DBG_TX_SOC_RX_R GPIO_141
+#define UART_FP_TX_SOC_RX GPIO_142
+#define UART_SOC_TX_DBG_RX_R GPIO_143
+#define RAM_ID_0 GPIO_144
+#define SOC_I2C_0_SCL GPIO_145
+#define SOC_I2C_0_SDA GPIO_146
+#define SOC_I2C_1_SCL GPIO_147
+#define SOC_I2C_1_SDA GPIO_148
+
 /* SPI Write protect */
-#define CROS_WP_GPIO GPIO_138
+#define CROS_WP_GPIO SOC_BIOS_WP_L
+
+/* EC sync irq */
+#define EC_SYNC_IRQ EC_SOC_INT_ODL
#endif /* __BASEBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h
index e49b7c4..bb7c349 100644
--- a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h
@@ -3,7 +3,7 @@
 #ifndef __BASEBOARD_VARIANTS_H__
 #define __BASEBOARD_VARIANTS_H__
-#include <gpio.h>
+#include <variant/gpio.h>
 #include <soc/pci_devs.h>
 #include <platform_descriptors.h>
diff --git a/src/mainboard/google/skyrim/variants/baseboard/smihandler.c b/src/mainboard/google/skyrim/variants/baseboard/smihandler.c
index ff59b2b..a6aa1ba 100644
--- a/src/mainboard/google/skyrim/variants/baseboard/smihandler.c
+++ b/src/mainboard/google/skyrim/variants/baseboard/smihandler.c
@@ -6,8 +6,8 @@
 #include <ec/google/chromeec/ec.h>
 #include <ec/google/chromeec/smm.h>
 #include <elog.h>
-#include <gpio.h>
 #include <variant/ec.h>
+#include <variant/gpio.h>
void mainboard_smi_sleep(u8 slp_typ)
 {
diff --git a/src/mainboard/google/skyrim/variants/baseboard/tpm_tis.c b/src/mainboard/google/skyrim/variants/baseboard/tpm_tis.c
index 7e513ef..645fd6a 100644
--- a/src/mainboard/google/skyrim/variants/baseboard/tpm_tis.c
+++ b/src/mainboard/google/skyrim/variants/baseboard/tpm_tis.c
@@ -1,9 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
#include <security/tpm/tis.h>
-#include <gpio.h>
+#include <variant/gpio.h>
int tis_plat_irq_status(void)
 {
-	return gpio_interrupt_status(GPIO_18);
+	return gpio_interrupt_status(GSC_SOC_INT_L);
 }
diff --git a/src/mainboard/google/skyrim/variants/crystaldrift/include/variant/gpio.h b/src/mainboard/google/skyrim/variants/crystaldrift/include/variant/gpio.h
new file mode 100644
index 0000000..dfaeec3
--- /dev/null
+++ b/src/mainboard/google/skyrim/variants/crystaldrift/include/variant/gpio.h
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
diff --git a/src/mainboard/google/skyrim/variants/frostflow/gpio.c b/src/mainboard/google/skyrim/variants/frostflow/gpio.c
index 45ead98..fb9c6ac 100644
--- a/src/mainboard/google/skyrim/variants/frostflow/gpio.c
+++ b/src/mainboard/google/skyrim/variants/frostflow/gpio.c
@@ -1,17 +1,15 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
-#include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
-#include <gpio.h>
+#include <variant/gpio.h>
/* GPIO configuration in ramstage */
 static const struct soc_amd_gpio override_gpio_table[] = {
-	/* EN_PWR_WWAN_X => CAM_PSW_L */
-	PAD_INT(GPIO_8, PULL_NONE, BOTH_EDGES, STATUS_DELIVERY),
-	/* SOC_SAR_INT_L => Unused */
+	PAD_INT(CAM_PSW_L, PULL_NONE, BOTH_EDGES, STATUS_DELIVERY),
+	/* SOC_SAR_INT_L(GPIO_17) => Unused */
    PAD_NC(GPIO_17),
-	/* WWAN_RST_L => Unused */
+	/* WWAN_RST(GPIO_42) => Unused */
    PAD_NC(GPIO_42),
 };
diff --git a/src/mainboard/google/skyrim/variants/frostflow/include/variant/gpio.h b/src/mainboard/google/skyrim/variants/frostflow/include/variant/gpio.h
new file mode 100644
index 0000000..8ef9f3a
--- /dev/null
+++ b/src/mainboard/google/skyrim/variants/frostflow/include/variant/gpio.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+
+/* EN_PWR_WWAN_X(GPIO_8) => CAM_PSW_L */
+#define CAM_PSW_L GPIO_8
+
+/* SOC_SAR_INT_L(GPIO_17) => Unused */
+/* WWAN_RST(GPIO_42) => Unused */
\ No newline at end of file
diff --git a/src/mainboard/google/skyrim/variants/markarth/gpio.c b/src/mainboard/google/skyrim/variants/markarth/gpio.c
index 9753179..a7dff10 100644
--- a/src/mainboard/google/skyrim/variants/markarth/gpio.c
+++ b/src/mainboard/google/skyrim/variants/markarth/gpio.c
@@ -1,22 +1,22 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
-#include <baseboard/gpio.h>
+
 #include <baseboard/variants.h>
-#include <gpio.h>
+#include <variant/gpio.h>
/* GPIO configuration in ramstage */
 static const struct soc_amd_gpio override_gpio_table[] = {
-	/* SOC_PEN_DETECT_ODL => Unused */
+	/* SOC_PEN_DETECT_ODL(GPIO_3) => Unused */
    PAD_NC(GPIO_3),
-	/* EN_PWR_FP => Unused */
+	/* EN_PWR_FP(GPIO_4) => Unused */
    PAD_NC(GPIO_4),
-	/* EN_PWR_WWAN_X => Unused */
+	/* EN_PWR_WWAN_X(GPIO_8) => Unused */
    PAD_NC(GPIO_8),
-	/* SOC_FP_INT_L => Unused */
+	/* SOC_FP_INT_L(GPIO_24) => Unused */
    PAD_NC(GPIO_24),
-	/* SD_AUX_RST_SOC_L => Unused */
+	/* SD_AUX_RST_SOC_L(GPIO_27) => Unused */
    PAD_NC(GPIO_27),
-	/* WWAN_RST_L => Unused */
+	/* WWAN_RST(GPIO_42) => Unused */
    PAD_NC(GPIO_42),
 };
diff --git a/src/mainboard/google/skyrim/variants/markarth/include/variant/gpio.h b/src/mainboard/google/skyrim/variants/markarth/include/variant/gpio.h
new file mode 100644
index 0000000..f30a952
--- /dev/null
+++ b/src/mainboard/google/skyrim/variants/markarth/include/variant/gpio.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+
+/* SOC_PEN_DETECT_ODL(GPIO_3) => Unused */
+/* EN_PWR_FP(GPIO_4) => Unused */
+/* EN_PWR_WWAN_X(GPIO_8) => Unused */
+/* SOC_FP_INT_L(GPIO_24) => Unused */
+/* SD_AUX_RST_SOC_L(GPIO_27) => Unused */
+/* WWAN_RST(GPIO_42) => Unused */
\ No newline at end of file
diff --git a/src/mainboard/google/skyrim/variants/markarth/port_descriptors.c b/src/mainboard/google/skyrim/variants/markarth/port_descriptors.c
index 330fc46..9e2702f 100644
--- a/src/mainboard/google/skyrim/variants/markarth/port_descriptors.c
+++ b/src/mainboard/google/skyrim/variants/markarth/port_descriptors.c
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
+#include <variant/gpio.h>
 #include <baseboard/variants.h>
 #include <console/console.h>
-#include <gpio.h>
 #include <soc/platform_descriptors.h>
 #include <types.h>
@@ -35,7 +35,7 @@
    	.link_aspm = ASPM_L1,
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
-		.gpio_group_id = GPIO_6,
+		.gpio_group_id = SSD_AUX_RST_L,
    	.clk_req = CLK_REQ1,
    },
 };
@@ -69,7 +69,7 @@
    	.link_aspm = ASPM_L1,
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
-		.gpio_group_id = GPIO_6,
+		.gpio_group_id = SSD_AUX_RST_L,
    	.clk_req = CLK_REQ0,
    },
 };
diff --git a/src/mainboard/google/skyrim/variants/skyrim/include/variant/gpio.h b/src/mainboard/google/skyrim/variants/skyrim/include/variant/gpio.h
new file mode 100644
index 0000000..dfaeec3
--- /dev/null
+++ b/src/mainboard/google/skyrim/variants/skyrim/include/variant/gpio.h
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
diff --git a/src/mainboard/google/skyrim/variants/winterhold/gpio.c b/src/mainboard/google/skyrim/variants/winterhold/gpio.c
index 340bfb6..f8fa98b 100644
--- a/src/mainboard/google/skyrim/variants/winterhold/gpio.c
+++ b/src/mainboard/google/skyrim/variants/winterhold/gpio.c
@@ -1,22 +1,19 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
-#include <baseboard/gpio.h>
+
 #include <baseboard/variants.h>
 #include <commonlib/helpers.h>
-#include <gpio.h>
+#include <variant/gpio.h>
/* GPIO configuration in ramstage */
 static const struct soc_amd_gpio override_gpio_table[] = {
-	/* SOC_PEN_DETECT_ODL */
+	/* SOC_PEN_DETECT_ODL(GPIO_3) => Unused */
    PAD_NC(GPIO_3),
-
-	/* EN_PWR_WWAN_X */
+	/* EN_PWR_WWAN_X(GPIO_8) => Unused */
    PAD_NC(GPIO_8),
-
-	/* SD_AUX_RST_SOC_L */
+	/* SD_AUX_RST_SOC_L(GPIO_27) => Unused */
    PAD_NC(GPIO_27),
-
-	/* WWAN_RST_L */
+	/* WWAN_RST(GPIO_42) => Unused */
    PAD_NC(GPIO_42),
};
diff --git a/src/mainboard/google/skyrim/variants/winterhold/include/variant/gpio.h b/src/mainboard/google/skyrim/variants/winterhold/include/variant/gpio.h
new file mode 100644
index 0000000..dfaeec3
--- /dev/null
+++ b/src/mainboard/google/skyrim/variants/winterhold/include/variant/gpio.h
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
diff --git a/src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c b/src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c
index 330fc46..9e2702f 100644
--- a/src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c
+++ b/src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
+#include <variant/gpio.h>
 #include <baseboard/variants.h>
 #include <console/console.h>
-#include <gpio.h>
 #include <soc/platform_descriptors.h>
 #include <types.h>
@@ -35,7 +35,7 @@
    	.link_aspm = ASPM_L1,
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
-		.gpio_group_id = GPIO_6,
+		.gpio_group_id = SSD_AUX_RST_L,
    	.clk_req = CLK_REQ1,
    },
 };
@@ -69,7 +69,7 @@
    	.link_aspm = ASPM_L1,
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
-		.gpio_group_id = GPIO_6,
+		.gpio_group_id = SSD_AUX_RST_L,
    	.clk_req = CLK_REQ0,
    },
 };
diff --git a/src/mainboard/google/skyrim/verstage.c b/src/mainboard/google/skyrim/verstage.c
index 1079e9b..8a9a2cc 100644
--- a/src/mainboard/google/skyrim/verstage.c
+++ b/src/mainboard/google/skyrim/verstage.c
@@ -3,11 +3,11 @@
 #include <amdblocks/acpimmio.h>
 #include <arch/io.h>
 #include <baseboard/variants.h>
-#include <gpio.h>
 #include <psp_verstage.h>
 #include <security/vboot/vboot_common.h>
 #include <soc/espi.h>
 #include <soc/southbridge.h>
+#include <variant/gpio.h>
void verstage_mainboard_early_init(void)
 {
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: If907478442ea7acb80b2e413926d173d188ce340
Gerrit-Change-Number: 74592
Gerrit-PatchSet: 1
Gerrit-Owner: Jon Murphy jpmurphy@google.com
Gerrit-Reviewer: Jason Nien jason.nien@amd.corp-partner.google.com
Gerrit-Reviewer: Martin Roth martin.roth@amd.corp-partner.google.com
Gerrit-Attention: Jason Nien jason.nien@amd.corp-partner.google.com
Gerrit-Attention: Martin Roth martin.roth@amd.corp-partner.google.com
Gerrit-MessageType: newchange



    