Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38229 )
Change subject: sb/intel/common: Add smbus_host_reset() ......................................................................
sb/intel/common: Add smbus_host_reset()
Change-Id: I3f6000df391295e2c0ce910a2a919a1dd3333519 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/include/device/smbus_host.h M src/southbridge/intel/bd82x6x/early_smbus.c M src/southbridge/intel/common/smbus.c M src/southbridge/intel/i82371eb/early_smbus.c M src/southbridge/intel/i82801dx/early_smbus.c M src/southbridge/intel/i82801gx/early_smbus.c M src/southbridge/intel/i82801ix/early_smbus.c M src/southbridge/intel/i82801jx/early_smbus.c M src/southbridge/intel/ibexpeak/early_smbus.c M src/southbridge/intel/lynxpoint/early_smbus.c 10 files changed, 28 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/38229/1
diff --git a/src/include/device/smbus_host.h b/src/include/device/smbus_host.h index 652bd96..8317e17 100644 --- a/src/include/device/smbus_host.h +++ b/src/include/device/smbus_host.h @@ -32,4 +32,9 @@ int do_i2c_eeprom_read(uintptr_t base, u8 device, u8 offset, size_t bytes, u8 *buf); int do_i2c_block_write(uintptr_t base, u8 device, size_t bytes, u8 *buf);
+/* Upstream API */ + +void smbus_host_reset(uintptr_t base); + + #endif diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c index 61625cc..c4b4663 100644 --- a/src/southbridge/intel/bd82x6x/early_smbus.c +++ b/src/southbridge/intel/bd82x6x/early_smbus.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */
-#include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> #include <device/pci_def.h> @@ -44,11 +43,8 @@ /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
- /* Disable interrupt generation. */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); + smbus_host_reset(SMBUS_IO_BASE);
- /* Clear any lingering errors, so transactions can run. */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); printk(BIOS_DEBUG, "SMBus controller enabled.\n"); }
diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c index d5853e5..b5141d7 100644 --- a/src/southbridge/intel/common/smbus.c +++ b/src/southbridge/intel/common/smbus.c @@ -92,6 +92,15 @@ host_outb(base, reg, value); }
+void smbus_host_reset(uintptr_t base) +{ + /* Disable interrupt generation. */ + host_outb(base, SMBHSTCTL, 0); + + /* Clear any lingering errors, so transactions can run. */ + host_update(base, SMBHSTSTAT, 0xff, 0); +} + static int host_completed(u8 status) { if (status & SMBHSTSTS_HOST_BUSY) diff --git a/src/southbridge/intel/i82371eb/early_smbus.c b/src/southbridge/intel/i82371eb/early_smbus.c index 4168a05..25267d7 100644 --- a/src/southbridge/intel/i82371eb/early_smbus.c +++ b/src/southbridge/intel/i82371eb/early_smbus.c @@ -15,7 +15,7 @@ */
#include <stdint.h> -#include <arch/io.h> +#include <console/console.h> #include <device/pci_ops.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -47,8 +47,9 @@ reg16 |= PCI_COMMAND_IO; pci_write_config16(dev, PCI_COMMAND, reg16);
- /* Clear any lingering errors, so the transaction will run. */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + smbus_host_reset(SMBUS_IO_BASE); + + printk(BIOS_DEBUG, "SMBus controller enabled\n"); }
int smbus_read_byte(u8 device, u8 address) diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c index 5e82ded..5549157 100644 --- a/src/southbridge/intel/i82801dx/early_smbus.c +++ b/src/southbridge/intel/i82801dx/early_smbus.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */
-#include <arch/io.h> #include <device/pci_ops.h> #include <device/pci_def.h> #include <console/console.h> @@ -27,17 +26,16 @@ { pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3);
- printk(BIOS_DEBUG, "SMBus controller enabled\n"); /* set smbus iobase */ pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); /* Set smbus enable */ pci_write_config8(dev, 0x40, 0x01); /* Set smbus iospace enable */ pci_write_config16(dev, 0x4, 0x01); - /* Disable interrupt generation */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); - /* clear any lingering errors, so the transaction will run */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + + smbus_host_reset(SMBUS_IO_BASE); + + printk(BIOS_DEBUG, "SMBus controller enabled\n"); }
int smbus_read_byte(unsigned int device, unsigned int address) diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c index 49056eb..59e03bc 100644 --- a/src/southbridge/intel/i82801gx/early_smbus.c +++ b/src/southbridge/intel/i82801gx/early_smbus.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */
-#include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> #include <device/pci_def.h> @@ -43,11 +42,8 @@ /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
- /* Disable interrupt generation. */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); + smbus_host_reset(SMBUS_IO_BASE);
- /* Clear any lingering errors, so transactions can run. */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); printk(BIOS_DEBUG, "SMBus controller enabled.\n"); }
diff --git a/src/southbridge/intel/i82801ix/early_smbus.c b/src/southbridge/intel/i82801ix/early_smbus.c index e067733..e541572 100644 --- a/src/southbridge/intel/i82801ix/early_smbus.c +++ b/src/southbridge/intel/i82801ix/early_smbus.c @@ -15,7 +15,6 @@ * GNU General Public License for more details. */
-#include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> #include <device/pci_def.h> @@ -45,11 +44,8 @@ /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
- /* Disable interrupt generation. */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); + smbus_host_reset(SMBUS_IO_BASE);
- /* Clear any lingering errors, so transactions can run. */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); printk(BIOS_DEBUG, "SMBus controller enabled.\n"); }
diff --git a/src/southbridge/intel/i82801jx/early_smbus.c b/src/southbridge/intel/i82801jx/early_smbus.c index f841355..f5084b5 100644 --- a/src/southbridge/intel/i82801jx/early_smbus.c +++ b/src/southbridge/intel/i82801jx/early_smbus.c @@ -15,7 +15,6 @@ * GNU General Public License for more details. */
-#include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> #include <device/pci_def.h> @@ -40,11 +39,8 @@ /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
- /* Disable interrupt generation. */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); + smbus_host_reset(SMBUS_IO_BASE);
- /* Clear any lingering errors, so transactions can run. */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); printk(BIOS_DEBUG, "SMBus controller enabled.\n"); }
diff --git a/src/southbridge/intel/ibexpeak/early_smbus.c b/src/southbridge/intel/ibexpeak/early_smbus.c index 0d18ed0..2d439f6 100644 --- a/src/southbridge/intel/ibexpeak/early_smbus.c +++ b/src/southbridge/intel/ibexpeak/early_smbus.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */
-#include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> #include <device/pci_def.h> @@ -44,11 +43,8 @@ /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
- /* Disable interrupt generation. */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); + smbus_host_reset(SMBUS_IO_BASE);
- /* Clear any lingering errors, so transactions can run. */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); printk(BIOS_DEBUG, "SMBus controller enabled.\n"); }
diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c index 61625cc..c4b4663 100644 --- a/src/southbridge/intel/lynxpoint/early_smbus.c +++ b/src/southbridge/intel/lynxpoint/early_smbus.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */
-#include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> #include <device/pci_def.h> @@ -44,11 +43,8 @@ /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
- /* Disable interrupt generation. */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); + smbus_host_reset(SMBUS_IO_BASE);
- /* Clear any lingering errors, so transactions can run. */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); printk(BIOS_DEBUG, "SMBus controller enabled.\n"); }
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38229
to look at the new patch set (#2).
Change subject: sb/intel/common: Add smbus_host_reset() ......................................................................
sb/intel/common: Add smbus_host_reset()
Change-Id: I3f6000df391295e2c0ce910a2a919a1dd3333519 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/include/device/smbus_host.h M src/southbridge/intel/bd82x6x/early_smbus.c M src/southbridge/intel/common/smbus.c M src/southbridge/intel/i82371eb/early_smbus.c M src/southbridge/intel/i82801dx/early_smbus.c M src/southbridge/intel/i82801gx/early_smbus.c M src/southbridge/intel/i82801ix/early_smbus.c M src/southbridge/intel/i82801jx/early_smbus.c M src/southbridge/intel/ibexpeak/early_smbus.c M src/southbridge/intel/lynxpoint/early_smbus.c 10 files changed, 28 insertions(+), 47 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/38229/2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38229 )
Change subject: sb/intel/common: Add smbus_host_reset() ......................................................................
Patch Set 3: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38229 )
Change subject: sb/intel/common: Add smbus_host_reset() ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38229/3/src/include/device/smbus_ho... File src/include/device/smbus_host.h:
https://review.coreboot.org/c/coreboot/+/38229/3/src/include/device/smbus_ho... PS3, Line 36: And this empty line?
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38229 )
Change subject: sb/intel/common: Add smbus_host_reset() ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38229/3/src/include/device/smbus_ho... File src/include/device/smbus_host.h:
https://review.coreboot.org/c/coreboot/+/38229/3/src/include/device/smbus_ho... PS3, Line 36:
And this empty line?
There was empty line 20 too.
Hello Patrick Rudolph, Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38229
to look at the new patch set (#4).
Change subject: sb/intel/common: Add smbus_host_reset() ......................................................................
sb/intel/common: Add smbus_host_reset()
Change-Id: I3f6000df391295e2c0ce910a2a919a1dd3333519 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/include/device/smbus_host.h M src/southbridge/intel/bd82x6x/early_smbus.c M src/southbridge/intel/common/smbus.c M src/southbridge/intel/i82371eb/early_smbus.c M src/southbridge/intel/i82801dx/early_smbus.c M src/southbridge/intel/i82801gx/early_smbus.c M src/southbridge/intel/i82801ix/early_smbus.c M src/southbridge/intel/i82801jx/early_smbus.c M src/southbridge/intel/ibexpeak/early_smbus.c M src/southbridge/intel/lynxpoint/early_smbus.c 10 files changed, 28 insertions(+), 47 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/38229/4
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38229 )
Change subject: sb/intel/common: Add smbus_host_reset() ......................................................................
Patch Set 4: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/38229/3/src/include/device/smbus_ho... File src/include/device/smbus_host.h:
https://review.coreboot.org/c/coreboot/+/38229/3/src/include/device/smbus_ho... PS3, Line 36:
There was empty line 20 too.
Ack
Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38229 )
Change subject: sb/intel/common: Add smbus_host_reset() ......................................................................
sb/intel/common: Add smbus_host_reset()
Change-Id: I3f6000df391295e2c0ce910a2a919a1dd3333519 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38229 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/include/device/smbus_host.h M src/southbridge/intel/bd82x6x/early_smbus.c M src/southbridge/intel/common/smbus.c M src/southbridge/intel/i82371eb/early_smbus.c M src/southbridge/intel/i82801dx/early_smbus.c M src/southbridge/intel/i82801gx/early_smbus.c M src/southbridge/intel/i82801ix/early_smbus.c M src/southbridge/intel/i82801jx/early_smbus.c M src/southbridge/intel/ibexpeak/early_smbus.c M src/southbridge/intel/lynxpoint/early_smbus.c 10 files changed, 28 insertions(+), 47 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/include/device/smbus_host.h b/src/include/device/smbus_host.h index 2aa160f..071eef0 100644 --- a/src/include/device/smbus_host.h +++ b/src/include/device/smbus_host.h @@ -32,4 +32,9 @@ int do_i2c_eeprom_read(uintptr_t base, u8 device, u8 offset, size_t bytes, u8 *buf); int do_i2c_block_write(uintptr_t base, u8 device, size_t bytes, u8 *buf);
+/* Upstream API */ + +void smbus_host_reset(uintptr_t base); + + #endif diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c index 61625cc..5ecce28 100644 --- a/src/southbridge/intel/bd82x6x/early_smbus.c +++ b/src/southbridge/intel/bd82x6x/early_smbus.c @@ -14,11 +14,9 @@ * GNU General Public License for more details. */
-#include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> #include <device/pci_def.h> -#include <southbridge/intel/common/smbus.h> #include <device/smbus_host.h> #include "pch.h"
@@ -44,11 +42,8 @@ /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
- /* Disable interrupt generation. */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); + smbus_host_reset(SMBUS_IO_BASE);
- /* Clear any lingering errors, so transactions can run. */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); printk(BIOS_DEBUG, "SMBus controller enabled.\n"); }
diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c index f294f31..f6805ad 100644 --- a/src/southbridge/intel/common/smbus.c +++ b/src/southbridge/intel/common/smbus.c @@ -92,6 +92,15 @@ host_outb(base, reg, value); }
+void smbus_host_reset(uintptr_t base) +{ + /* Disable interrupt generation. */ + host_outb(base, SMBHSTCTL, 0); + + /* Clear any lingering errors, so transactions can run. */ + host_and_or(base, SMBHSTSTAT, 0xff, 0); +} + static int host_completed(u8 status) { if (status & SMBHSTSTS_HOST_BUSY) diff --git a/src/southbridge/intel/i82371eb/early_smbus.c b/src/southbridge/intel/i82371eb/early_smbus.c index 4168a05..917a3b4 100644 --- a/src/southbridge/intel/i82371eb/early_smbus.c +++ b/src/southbridge/intel/i82371eb/early_smbus.c @@ -15,12 +15,11 @@ */
#include <stdint.h> -#include <arch/io.h> +#include <console/console.h> #include <device/pci_ops.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_def.h> -#include <southbridge/intel/common/smbus.h> #include <device/smbus_host.h> #include "i82371eb.h"
@@ -47,8 +46,9 @@ reg16 |= PCI_COMMAND_IO; pci_write_config16(dev, PCI_COMMAND, reg16);
- /* Clear any lingering errors, so the transaction will run. */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + smbus_host_reset(SMBUS_IO_BASE); + + printk(BIOS_DEBUG, "SMBus controller enabled\n"); }
int smbus_read_byte(u8 device, u8 address) diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c index 5e82ded..77b0aa0 100644 --- a/src/southbridge/intel/i82801dx/early_smbus.c +++ b/src/southbridge/intel/i82801dx/early_smbus.c @@ -14,11 +14,9 @@ * GNU General Public License for more details. */
-#include <arch/io.h> #include <device/pci_ops.h> #include <device/pci_def.h> #include <console/console.h> -#include <southbridge/intel/common/smbus.h> #include <device/smbus_host.h>
#include "i82801dx.h" @@ -27,17 +25,16 @@ { pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3);
- printk(BIOS_DEBUG, "SMBus controller enabled\n"); /* set smbus iobase */ pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); /* Set smbus enable */ pci_write_config8(dev, 0x40, 0x01); /* Set smbus iospace enable */ pci_write_config16(dev, 0x4, 0x01); - /* Disable interrupt generation */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); - /* clear any lingering errors, so the transaction will run */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); + + smbus_host_reset(SMBUS_IO_BASE); + + printk(BIOS_DEBUG, "SMBus controller enabled\n"); }
int smbus_read_byte(unsigned int device, unsigned int address) diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c index 49056eb..60fcceb 100644 --- a/src/southbridge/intel/i82801gx/early_smbus.c +++ b/src/southbridge/intel/i82801gx/early_smbus.c @@ -14,11 +14,9 @@ * GNU General Public License for more details. */
-#include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> #include <device/pci_def.h> -#include <southbridge/intel/common/smbus.h> #include <device/smbus_host.h> #include "i82801gx.h"
@@ -43,11 +41,8 @@ /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
- /* Disable interrupt generation. */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); + smbus_host_reset(SMBUS_IO_BASE);
- /* Clear any lingering errors, so transactions can run. */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); printk(BIOS_DEBUG, "SMBus controller enabled.\n"); }
diff --git a/src/southbridge/intel/i82801ix/early_smbus.c b/src/southbridge/intel/i82801ix/early_smbus.c index e067733..4286760 100644 --- a/src/southbridge/intel/i82801ix/early_smbus.c +++ b/src/southbridge/intel/i82801ix/early_smbus.c @@ -15,12 +15,10 @@ * GNU General Public License for more details. */
-#include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#include <southbridge/intel/common/smbus.h> #include <device/smbus_host.h> #include "i82801ix.h"
@@ -45,11 +43,8 @@ /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
- /* Disable interrupt generation. */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); + smbus_host_reset(SMBUS_IO_BASE);
- /* Clear any lingering errors, so transactions can run. */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); printk(BIOS_DEBUG, "SMBus controller enabled.\n"); }
diff --git a/src/southbridge/intel/i82801jx/early_smbus.c b/src/southbridge/intel/i82801jx/early_smbus.c index f841355..594400f 100644 --- a/src/southbridge/intel/i82801jx/early_smbus.c +++ b/src/southbridge/intel/i82801jx/early_smbus.c @@ -15,11 +15,9 @@ * GNU General Public License for more details. */
-#include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> #include <device/pci_def.h> -#include <southbridge/intel/common/smbus.h> #include <device/smbus_host.h> #include "i82801jx.h"
@@ -40,11 +38,8 @@ /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
- /* Disable interrupt generation. */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); + smbus_host_reset(SMBUS_IO_BASE);
- /* Clear any lingering errors, so transactions can run. */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); printk(BIOS_DEBUG, "SMBus controller enabled.\n"); }
diff --git a/src/southbridge/intel/ibexpeak/early_smbus.c b/src/southbridge/intel/ibexpeak/early_smbus.c index 0d18ed0..fdf0c32 100644 --- a/src/southbridge/intel/ibexpeak/early_smbus.c +++ b/src/southbridge/intel/ibexpeak/early_smbus.c @@ -14,11 +14,9 @@ * GNU General Public License for more details. */
-#include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> #include <device/pci_def.h> -#include <southbridge/intel/common/smbus.h> #include <device/smbus_host.h> #include "pch.h"
@@ -44,11 +42,8 @@ /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
- /* Disable interrupt generation. */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); + smbus_host_reset(SMBUS_IO_BASE);
- /* Clear any lingering errors, so transactions can run. */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); printk(BIOS_DEBUG, "SMBus controller enabled.\n"); }
diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c index 61625cc..5ecce28 100644 --- a/src/southbridge/intel/lynxpoint/early_smbus.c +++ b/src/southbridge/intel/lynxpoint/early_smbus.c @@ -14,11 +14,9 @@ * GNU General Public License for more details. */
-#include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> #include <device/pci_def.h> -#include <southbridge/intel/common/smbus.h> #include <device/smbus_host.h> #include "pch.h"
@@ -44,11 +42,8 @@ /* Set SMBus I/O space enable. */ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
- /* Disable interrupt generation. */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); + smbus_host_reset(SMBUS_IO_BASE);
- /* Clear any lingering errors, so transactions can run. */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); printk(BIOS_DEBUG, "SMBus controller enabled.\n"); }
-
Angel Pons (Code Review) -
Kyösti Mälkki (Code Review)