Change in coreboot[master]: soc/intel/tigerlake: Configure TCSS D3Cold for pre-QS and QS platforms
John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43980 )
Change subject: soc/intel/tigerlake: Configure TCSS D3Cold for pre-QS and QS platforms ......................................................................
soc/intel/tigerlake: Configure TCSS D3Cold for pre-QS and QS platforms
There are known limitation for D3Colde enabling on pre-QS platform. This change reads cpu id and disables TCSS D3Cold for pre-QS platform. For QS platform, D3Cold enabling will be based on mainboard configuration.
BUG=None TEST=Verified D3Cold is disabled for pre-QS (cpu:806c0) and enabled for QS (cpu:0x806c1) if platform TcssD3ColdeEnable is set to 1.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I534ddfefcd182f5b35aa5e8b461f0920d375a66d --- M src/soc/intel/tigerlake/fsp_params.c 1 file changed, 7 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/43980/1
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 885a6f9..0c8344e 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -9,6 +9,7 @@ #include <fsp/util.h> #include <intelblocks/cse.h> #include <intelblocks/lpss.h> +#include <intelblocks/mp_init.h> #include <intelblocks/xdci.h> #include <intelpch/lockdown.h> #include <security/vboot/vboot_common.h> @@ -85,6 +86,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { int i; + uint32_t cpu_id; FSP_S_CONFIG *params = &supd->FspsConfig;
struct device *dev; @@ -114,7 +116,11 @@
/* D3Hot and D3Cold for TCSS */ params->D3HotEnable = config->TcssD3HotEnable; - params->D3ColdEnable = config->TcssD3ColdEnable; + cpu_id = cpu_get_cpuid(); + if (cpu_id == CPUID_TIGERLAKE_A0) + params->D3ColdEnable = 0; + else + params->D3ColdEnable = config->TcssD3ColdEnable;
params->TcssAuxOri = config->TcssAuxOri; for (i = 0; i < 8; i++)
Hello Wonkyu Kim, Shreesh Chhabbi, Caveh Jalali, Ravishankar Sarawadi, Tim Wawrzynczak, Shamile Khan, Patrick Rudolph, Divya S Sasidharan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43980
to look at the new patch set (#2).
Change subject: soc/intel/tigerlake: Configure TCSS D3Cold for pre-QS and QS platforms ......................................................................
soc/intel/tigerlake: Configure TCSS D3Cold for pre-QS and QS platforms
There are known limitation for D3Cold enabling on pre-QS platform. This change reads cpu id and disables TCSS D3Cold for pre-QS platform. For QS platform, D3Cold enabling will be based on mainboard configuration.
BUG=None TEST=Verified D3Cold is disabled for pre-QS (cpu:806c0) and enabled for QS (cpu:0x806c1) if platform TcssD3ColdEnable is set to 1.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I534ddfefcd182f5b35aa5e8b461f0920d375a66d --- M src/soc/intel/tigerlake/fsp_params.c 1 file changed, 7 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/43980/2
Ravishankar Sarawadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43980 )
Change subject: soc/intel/tigerlake: Configure TCSS D3Cold for pre-QS and QS platforms ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43980/2/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/43980/2/src/soc/intel/tigerlake/fsp... PS2, Line 119: cpu_id = cpu_get_cpuid(); : if (cpu_id == CPUID_TIGERLAKE_A0) : params->D3ColdEnable = 0; : else Shouldn't it be handled in DT as done in https://review.coreboot.org/c/coreboot/+/43621
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43980 )
Change subject: soc/intel/tigerlake: Configure TCSS D3Cold for pre-QS and QS platforms ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43980/2/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/43980/2/src/soc/intel/tigerlake/fsp... PS2, Line 119: cpu_id = cpu_get_cpuid(); : if (cpu_id == CPUID_TIGERLAKE_A0) : params->D3ColdEnable = 0; : else
Shouldn't it be handled in DT as done in https://review.coreboot. […]
Depends on if we will have any variant that has some boards with pre-QS and other with QS.
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43980 )
Change subject: soc/intel/tigerlake: Configure TCSS D3Cold for pre-QS and QS platforms ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43980/2/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/43980/2/src/soc/intel/tigerlake/fsp... PS2, Line 119: cpu_id = cpu_get_cpuid(); : if (cpu_id == CPUID_TIGERLAKE_A0) : params->D3ColdEnable = 0; : else
Depends on if we will have any variant that has some boards with pre-QS and other with QS.
we have dedicated variants for ES2 vs. QS SoCs - i.e. A0 vs. B0 silicon. is there additional granularity we need to handle that can't be addressed with the variant specific overridetree.cb?
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43980 )
Change subject: soc/intel/tigerlake: Configure TCSS D3Cold for pre-QS and QS platforms ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43980/2/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/43980/2/src/soc/intel/tigerlake/fsp... PS2, Line 119: cpu_id = cpu_get_cpuid(); : if (cpu_id == CPUID_TIGERLAKE_A0) : params->D3ColdEnable = 0; : else
we have dedicated variants for ES2 vs. QS SoCs - i.e. A0 vs. B0 silicon. […]
As this is only A0 limitaion, I think it's better handle by devicetree rather than soc code change.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43980 )
Change subject: soc/intel/tigerlake: Configure TCSS D3Cold for pre-QS and QS platforms ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43980/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43980/2//COMMIT_MSG@9 PS2, Line 9: limitation limitation*s*
https://review.coreboot.org/c/coreboot/+/43980/2/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/43980/2/src/soc/intel/tigerlake/fsp... PS2, Line 120: (cpu_id == CPUID_TIGERLAKE_A0) Maybe encapsulate this in a function `static bool can_enable_tcss_d3cold(void)`? This would result in a cleaner statement here:
params->D3ColdEnable = can_enable_tcss_d3cold() && config->TcssD3ColdEnable;
Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Caveh Jalali, Shreesh Chhabbi, Ravishankar Sarawadi, Tim Wawrzynczak, Shamile Khan, Patrick Rudolph, Divya S Sasidharan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43980
to look at the new patch set (#3).
Change subject: soc/intel/tigerlake: Configure TCSS D3Cold for pre-QS and QS platforms ......................................................................
soc/intel/tigerlake: Configure TCSS D3Cold for pre-QS and QS platforms
There are known limitations for D3Cold enabling on pre-QS platform. This change reads cpu id and disables TCSS D3Cold for pre-QS platform. For QS platform, D3Cold enabling will be based on mainboard configuration.
BUG=None TEST=Verified D3Cold is disabled for pre-QS (cpu:806c0) and enabled for QS (cpu:0x806c1) if platform TcssD3ColdEnable is set to 1.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I534ddfefcd182f5b35aa5e8b461f0920d375a66d --- M src/soc/intel/tigerlake/fsp_params.c 1 file changed, 7 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/43980/3
John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43980 )
Change subject: soc/intel/tigerlake: Configure TCSS D3Cold for pre-QS and QS platforms ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43980/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43980/2//COMMIT_MSG@9 PS2, Line 9: limitation
limitation*s*
Done
https://review.coreboot.org/c/coreboot/+/43980/2/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/43980/2/src/soc/intel/tigerlake/fsp... PS2, Line 119: cpu_id = cpu_get_cpuid(); : if (cpu_id == CPUID_TIGERLAKE_A0) : params->D3ColdEnable = 0; : else
Depends on if we will have any variant that has some boards with pre-QS and other with QS.
If is clean to rebase CB:43621 on CB:43980 and update CB:43621 only with baseboard/devicetree.cb register "TcssD3ColdEnable" = "1". Then no need to update all those variants override.cb. CB:43980 works with all existing TGLRVP configuration as well.
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43980 )
Change subject: soc/intel/tigerlake: Configure TCSS D3Cold for pre-QS and QS platforms ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43980/3/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/43980/3/src/soc/intel/tigerlake/fsp... PS3, Line 123: TcssD3ColdEnable if the expected setting is for D3ColdEnable to be enabled, maybe we should have a TcssD3ColdDisable similar to what we did for PchPwrOptEnable.
John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43980 )
Change subject: soc/intel/tigerlake: Configure TCSS D3Cold for pre-QS and QS platforms ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43980/2/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/43980/2/src/soc/intel/tigerlake/fsp... PS2, Line 120: (cpu_id == CPUID_TIGERLAKE_A0)
Maybe encapsulate this in a function `static bool can_enable_tcss_d3cold(void)`? This would result i […]
Not sure whether we need to create a function for this one line of code. Others put comments to consider configuring D3Cold only through devicetree/override. Let us wait for the decision.
https://review.coreboot.org/c/coreboot/+/43980/3/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/43980/3/src/soc/intel/tigerlake/fsp... PS3, Line 123: TcssD3ColdEnable
if the expected setting is for D3ColdEnable to be enabled, […]
D3ColdEnable setting is expected to be enabled. There is only D3ColdEnable in fsp upd and no D3ColdDisable. So it appears no need to consider adding TcssD3ColdDisable into soc_intel_tigerlake_config structure. This patch would disable D3Cold for pre-QS and enable D3Cold for QS if platform's TcssD3ColdEnable is set "1", which is expected.
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43980 )
Change subject: soc/intel/tigerlake: Configure TCSS D3Cold for pre-QS and QS platforms ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43980/3/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/43980/3/src/soc/intel/tigerlake/fsp... PS3, Line 123: TcssD3ColdEnable
D3ColdEnable setting is expected to be enabled. […]
if we change TcssD3ColdEnable to TcssD3ColdDisable:
params->D3ColdEnable = !!config->TcssD3ColdDisble
we won't need a device tree entry at all unless someone needs to explicitly disable it for some exceptional case.
John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43980 )
Change subject: soc/intel/tigerlake: Configure TCSS D3Cold for pre-QS and QS platforms ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43980/3/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/43980/3/src/soc/intel/tigerlake/fsp... PS3, Line 123: TcssD3ColdEnable
if we change TcssD3ColdEnable to TcssD3ColdDisable: […]
Typically soc_intel_tigerlake_config elements are aligned with fsp upd. Sure, TcssD3ColdEnable can be changed to TcssD3ColdDisable to fit params->D3ColdEnable = !!config->TcssD3ColdDisble. But then it would need additional patches orderly across soc and mainboards in order to avoid build break because we can not simply rename TcssD3ColdEnable to TcssD3ColdDisable.
John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43980 )
Change subject: soc/intel/tigerlake: Configure TCSS D3Cold for pre-QS and QS platforms ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43980/3/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/43980/3/src/soc/intel/tigerlake/fsp... PS3, Line 123: TcssD3ColdEnable
Typically soc_intel_tigerlake_config elements are aligned with fsp upd. […]
I mean we need to remove all TcssD3ColdEnable across both of Volteer and TGLRVP first. Then update this patch.
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43980 )
Change subject: soc/intel/tigerlake: Configure TCSS D3Cold for pre-QS and QS platforms ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43980/3/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/43980/3/src/soc/intel/tigerlake/fsp... PS3, Line 123: TcssD3ColdEnable
I mean we need to remove all TcssD3ColdEnable across both of Volteer and TGLRVP first. […]
i think it's reasonable to include the 1-line edits to the 3 devicetree.cb files with this patch for consistency. the only change in the device trees will be to remove the TcssD3ColdEnable lines since they'll become redundant.
the beauty is that we can eliminate the TcssD3ColdEnable line from all device trees unless there are exceptional circumstances.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43980 )
Change subject: soc/intel/tigerlake: Configure TCSS D3Cold for pre-QS and QS platforms ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43980/3/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/43980/3/src/soc/intel/tigerlake/fsp... PS3, Line 123: TcssD3ColdEnable
i think it's reasonable to include the 1-line edits to the 3 devicetree.cb […]
If TCSS D3Cold is expected to be enabled in most cases, then I agree that we should rename it. Only one negation, though:
params->D3ColdEnable = !config->TcssD3ColdDisable;
We should also rename TcssD3HotEnable, too.
John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43980 )
Change subject: soc/intel/tigerlake: Configure TCSS D3Cold for pre-QS and QS platforms ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43980/3/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/43980/3/src/soc/intel/tigerlake/fsp... PS3, Line 123: TcssD3ColdEnable
If TCSS D3Cold is expected to be enabled in most cases, then I agree that we should rename it. […]
Agreed. Ravi, can you update CB:43621 to remove TcssD3HotEnable and TcssD3ColdEnable for Volteer/variants? I will add another patch to handle TGLRVP UP3 and UP4 and rebase this patch with further update.
Ravishankar Sarawadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43980 )
Change subject: soc/intel/tigerlake: Configure TCSS D3Cold for pre-QS and QS platforms ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43980/3/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/43980/3/src/soc/intel/tigerlake/fsp... PS3, Line 123: TcssD3ColdEnable
Agreed. […]
CB:43621 abandoned, John.
Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Caveh Jalali, Shreesh Chhabbi, Ravishankar Sarawadi, Tim Wawrzynczak, Shamile Khan, Patrick Rudolph, Divya S Sasidharan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43980
to look at the new patch set (#4).
Change subject: soc/intel/tigerlake: Configure TCSS D3Hot and D3Cold ......................................................................
soc/intel/tigerlake: Configure TCSS D3Hot and D3Cold
Update configuration for both of TCSS D3Hot and D3Cold. It is expected D3Hot is enabled for all platforms. Because there are known limitations for D3Cold enabling on pre-QS platform, this change reads cpu id and disables D3Cold for pre-QS platform. For QS platform, D3Cold is configured to be enabled.
BUG=None TEST=Verified D3Hot is enabled, D3Cold is disabled for pre-QS (cpu:806c0) and enabled for QS (cpu:0x806c1).
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I534ddfefcd182f5b35aa5e8b461f0920d375a66d --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c 2 files changed, 10 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/43980/4
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43980 )
Change subject: soc/intel/tigerlake: Configure TCSS D3Hot and D3Cold ......................................................................
Patch Set 4: Code-Review+2
Divya S Sasidharan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43980 )
Change subject: soc/intel/tigerlake: Configure TCSS D3Hot and D3Cold ......................................................................
Patch Set 4: Code-Review+1
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43980 )
Change subject: soc/intel/tigerlake: Configure TCSS D3Hot and D3Cold ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43980/4/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/43980/4/src/soc/intel/tigerlake/fsp... PS4, Line 120: if (cpu_id == CPUID_TIGERLAKE_A0) : params->D3ColdEnable = 0; Do we still need this condition which we don't need eventually? I thought devicetree change with TcssD3ColdDisable should handle this for only few varient with Ax version.
John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43980 )
Change subject: soc/intel/tigerlake: Configure TCSS D3Hot and D3Cold ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43980/4/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/43980/4/src/soc/intel/tigerlake/fsp... PS4, Line 120: if (cpu_id == CPUID_TIGERLAKE_A0) : params->D3ColdEnable = 0;
Do we still need this condition which we don't need eventually? […]
Without this check and configuration, A stepping D3Cold will be wrongly enabled now because no TcssD3ColdDisable is set across all platforms (Volteer/variants, RVP).
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43980 )
Change subject: soc/intel/tigerlake: Configure TCSS D3Hot and D3Cold ......................................................................
Patch Set 4: Code-Review+2
Checked it with Google, we'll add condition check in fsp_param.c for now and we'll check again if we can remove the condition by checking stepping info for active varients.
Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43980 )
Change subject: soc/intel/tigerlake: Configure TCSS D3Hot and D3Cold ......................................................................
soc/intel/tigerlake: Configure TCSS D3Hot and D3Cold
Update configuration for both of TCSS D3Hot and D3Cold. It is expected D3Hot is enabled for all platforms. Because there are known limitations for D3Cold enabling on pre-QS platform, this change reads cpu id and disables D3Cold for pre-QS platform. For QS platform, D3Cold is configured to be enabled.
BUG=None TEST=Verified D3Hot is enabled, D3Cold is disabled for pre-QS (cpu:806c0) and enabled for QS (cpu:0x806c1).
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: I534ddfefcd182f5b35aa5e8b461f0920d375a66d Reviewed-on: https://review.coreboot.org/c/coreboot/+/43980 Reviewed-by: Caveh Jalali caveh@chromium.org Reviewed-by: Divya S Sasidharan divya.s.sasidharan@intel.com Reviewed-by: Wonkyu Kim wonkyu.kim@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c 2 files changed, 10 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Divya S Sasidharan: Looks good to me, but someone else must approve Caveh Jalali: Looks good to me, approved Wonkyu Kim: Looks good to me, approved
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 812dbac..dc910ff 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -79,9 +79,9 @@ /* Enable S0iX support */ int s0ix_enable; /* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */ - uint8_t TcssD3HotEnable; + uint8_t TcssD3HotDisable; /* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */ - uint8_t TcssD3ColdEnable; + uint8_t TcssD3ColdDisable;
/* Enable DPTF support */ int dptf_enable; diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 79ce04b..517d771 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -9,6 +9,7 @@ #include <fsp/util.h> #include <intelblocks/cse.h> #include <intelblocks/lpss.h> +#include <intelblocks/mp_init.h> #include <intelblocks/xdci.h> #include <intelpch/lockdown.h> #include <security/vboot/vboot_common.h> @@ -85,6 +86,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { int i; + uint32_t cpu_id; FSP_S_CONFIG *params = &supd->FspsConfig;
struct device *dev; @@ -110,8 +112,12 @@ }
/* D3Hot and D3Cold for TCSS */ - params->D3HotEnable = config->TcssD3HotEnable; - params->D3ColdEnable = config->TcssD3ColdEnable; + params->D3HotEnable = !config->TcssD3HotDisable; + cpu_id = cpu_get_cpuid(); + if (cpu_id == CPUID_TIGERLAKE_A0) + params->D3ColdEnable = 0; + else + params->D3ColdEnable = !config->TcssD3ColdDisable;
params->TcssAuxOri = config->TcssAuxOri; for (i = 0; i < 8; i++)
-
Angel Pons (Code Review) -
Caveh Jalali (Code Review)
-
Divya S Sasidharan (Code Review)
-
John Zhao (Code Review)
-
Nick Vaccaro (Code Review)
-
Ravishankar Sarawadi (Code Review)
-
Tim Wawrzynczak (Code Review)
-
Wonkyu Kim (Code Review)