Attention is currently required from: Hung-Te Lin, Kiwi Liu, Mengqi Zhang, Yu-Ping Wu.
Yidi Lin has posted comments on this change by Kiwi Liu. ( https://review.coreboot.org/c/coreboot/+/84298?usp=email )
Change subject: UPSTREAM: soc/mediatek/common: Fix eMMC clock ......................................................................
Patch Set 3:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84298/comment/3620ad95_e8ff6d1e?usp... : PS3, Line 7: UPSTREAM: remove
https://review.coreboot.org/c/coreboot/+/84298/comment/dc8e658a_be65de96?usp... : PS3, Line 9: Mediatek SOC start operating at eMMC clock around 2 MHz : right after power-on. : In JEDEC spec, this period is 400 kHz or less. ``` MediaTek SoC operates eMMC clock around 2 MHz right after power-on. In JEDEC spec, the operating clock should be 400 kHz or less. ``` Please wrap the text at 72 characters.
https://review.coreboot.org/c/coreboot/+/84298/comment/e9a3dedc_48b28991?usp... : PS3, Line 14: emerge-corsola coreboot I don't think this is a proper test method.
https://review.coreboot.org/c/coreboot/+/84298/comment/822335c4_4cac224f?usp... : PS3, Line 19: Tested-by: Konishi Yoshi konishi_yoshi@fujitsu.corp-partner.google.com : Reviewed-by: Konishi Yoshi konishi_yoshi@fujitsu.corp-partner.google.com remove