Michał Żygowski has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72072?usp=email )
(
1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/apollolake: Select PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B ......................................................................
soc/intel/apollolake: Select PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B
Certain chipsets/SoCs like Apollo Lake use GEN_PMCON_B for periodic SMI rate selection unlike other chipsets which use GEN_PMCON_A. Select PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B to indicate the register difference.
Based on Apollo Lake datasheet Vol. 3 Revision 005: https://cdrdv2.intel.com/v1/dl/getContent/334819
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: If182e1285ad6bd3f7c54760440010c50f57f7013 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72072 Reviewed-by: Sean Rhodes sean@starlabs.systems Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/apollolake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Sean Rhodes: Looks good to me, approved
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 395d7aa6..1157f06 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -64,6 +64,7 @@ select PCIEXP_COMMON_CLOCK select PCIEXP_CLK_PM select PCIEXP_L1_SUB_STATE + select PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B select PLATFORM_USES_FSP2_0 select PMC_INVALID_READ_AFTER_WRITE select PMC_GLOBAL_RESET_ENABLE_LOCK