[XL] Change in coreboot[master]: soc/intel/xeon_sp/spr: add ACPI code

[Jian-Ming Wang (Code Review)]

Attention is currently required from: Patrick Rudolph, Jonathan Zhang, Simon Chou, TimLiu-SMCI, Johnny Lin, Christian Walter, Shuming Chu (Shuming), Arthur Heymans.

Jian-Ming Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71967 )

Change subject: soc/intel/xeon_sp/spr: add ACPI code
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Patch Set 13:

(1 comment)

File src/soc/intel/xeon_sp/spr/romstage.c:

https://review.coreboot.org/c/coreboot/+/71967/comment/ebb38984_56e9c961 
PS2, Line 177:  0x3F8;
> Have it depend on the port coreboot uses.

SerialIoUartDebugIoBase in FSPM_UPD is used to control the debug message from Intel FSP. The correct configuration is depending on mainboard design. However, the romstage in soc layer only take care of the critical common configuration. The mainboard specific part should be override or further configured by romstage (mainboard_romstage_entry) in mainboard layer.
Please reference the example to mainboard_config_upd in src/mainboard/ocp/deltalake.romstage.c.