New patch to review for coreboot: 1f19869 mc146818: Change read_option to use cmos_layout.bin

[Vladimir Serbinenko]

Vladimir Serbinenko ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4828

-gerrit

commit 1f198694eefcb9d7d8a94ef837ab414169b750fe
Author: Vladimir Serbinenko 
Date:   Sun Jan 26 23:47:03 2014 +0100

mc146818: Change read_option to use cmos_layout.bin

To simplify updating existing image.

Change-Id: I6e163c05877e8b205143599197ba7f45fece0227
    Signed-off-by: Vladimir Serbinenko 
---
 src/drivers/pc80/mc146818rtc_early.c  | 40 +++++++++++++++++++++++++++++++----
 src/include/boot/coreboot_tables.h    | 19 +++++++++++++++++
 src/include/pc80/mc146818rtc.h        |  5 ++---
 src/lib/uart8250.c                    |  6 +-----
 src/lib/uart8250mem.c                 |  5 +----
 src/northbridge/intel/e7520/raminit.c |  7 +-----
 src/northbridge/intel/e7525/raminit.c |  7 +-----
 7 files changed, 61 insertions(+), 28 deletions(-)

diff --git a/src/drivers/pc80/mc146818rtc_early.c b/src/drivers/pc80/mc146818rtc_early.c
index 0652f27..bb6caf1 100644
--- a/src/drivers/pc80/mc146818rtc_early.c
+++ b/src/drivers/pc80/mc146818rtc_early.c
@@ -1,6 +1,13 @@
 #include <stdint.h>
 #include <pc80/mc146818rtc.h>
 #include <fallback.h>
+#ifdef __ROMCC__
+#include <arch/cbfs.h>
+#else
+#include <cbfs.h>
+#endif
+#include <boot/coreboot_tables.h>
+
 #if CONFIG_USE_OPTION_TABLE
 #include "option_table.h"
 #endif
@@ -92,12 +99,37 @@ static inline int do_normal_boot(void)
    return (byte & (1<<1));
 }

-unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def)
+unsigned read_option(const char *name, unsigned def)
 {
 #if CONFIG_USE_OPTION_TABLE
-	unsigned byte;
-	byte = cmos_read(start/8);
-	return (byte >> (start & 7U)) & ((1U << size) - 1U);
+	struct cmos_option_table *ct;
+	struct cmos_entries *ce;
+
+#ifdef __ROMCC__
+	ct = (struct cmos_option_table *)walkcbfs("cmos_layout.bin");
+#else
+	ct = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "cmos_layout.bin",
+				   CBFS_COMPONENT_CMOS_LAYOUT, NULL);
+#endif
+
+	if (!ct)
+		return def;
+
+	ce=(struct cmos_entries*)((unsigned char *)ct + ct->header_length);
+	for(;ce->tag==LB_TAG_OPTION;
+		ce=(struct cmos_entries*)((unsigned char *)ce + ce->size)) {
+		unsigned byte;
+		unsigned i;
+		for (i = 0; name[i] && i < CMOS_MAX_NAME_LENGTH; i++)
+			if (name[i] != ce->name[i])
+				goto next_option;
+		byte = cmos_read(ce->bit/8);
+		byte >>= (ce->bit & 7U);
+
+		return (byte) & ((1U << ce->length) - 1U);
+	next_option:;
+	}
+	return def;
 #else
    return def;
 #endif
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h
index aa8409a..9d46223 100644
--- a/src/include/boot/coreboot_tables.h
+++ b/src/include/boot/coreboot_tables.h
@@ -43,6 +43,7 @@
  * See also: util/lbtdump/lbtdump.c
  */

+#ifndef __ROMCC__
 struct lb_uint64 {
    uint32_t lo;
    uint32_t hi;
@@ -64,6 +65,8 @@ static inline struct lb_uint64 pack_lb64(uint64_t value)
    return result;
 }

+#endif
+
 struct lb_header
 {
    uint8_t  signature[4]; /* LBIO */
@@ -89,6 +92,8 @@ struct lb_record {

#define LB_TAG_MEMORY		0x0001

+#ifndef __ROMCC__
+
 struct lb_memory_range {
    struct lb_uint64 start;
    struct lb_uint64 size;
@@ -115,6 +120,8 @@ struct lb_hwrpb {
    uint64_t hwrpb;
 };

+#endif
+
 #define LB_TAG_MAINBOARD	0x0003
 struct lb_mainboard {
    uint32_t tag;
@@ -168,6 +175,8 @@ struct lb_console {
 #define LB_TAG_CONSOLE_EHCI		5
 #define LB_TAG_CONSOLE_SERIAL8250MEM	6

+#ifndef __ROMCC__
+
 #define LB_TAG_FORWARD		0x0011
 struct lb_forward {
    uint32_t tag;
@@ -195,6 +204,8 @@ struct lb_framebuffer {
    uint8_t reserved_mask_size;
 };

+#endif
+
 #define LB_TAG_GPIO	0x0013

struct lb_gpio {
@@ -213,6 +224,8 @@ struct lb_gpios {
    struct lb_gpio gpios[0];
 };

+#ifndef __ROMCC__
+
 #define LB_TAG_VDAT	0x0015
 struct lb_vdat {
    uint32_t tag;
@@ -250,6 +263,8 @@ struct lb_vboot_handoff {
    uint32_t vboot_handoff_size;
 };

+#endif
+
 #define LB_TAG_X86_ROM_MTRR	0x0021
 struct lb_x86_rom_mtrr {
    uint32_t tag;
@@ -333,6 +348,8 @@ struct	cmos_checksum {

/* function prototypes for building the coreboot table */

+#ifndef __ROMCC__
+
 unsigned long write_coreboot_table(
    unsigned long low_table_start, unsigned long low_table_end,
    unsigned long rom_table_start, unsigned long rom_table_end);
@@ -347,4 +364,6 @@ struct lb_memory *get_lb_mem(void);

void fill_lb_gpios(struct lb_gpios *gpios);

+#endif
+
 #endif /* COREBOOT_TABLES_H */
diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h
index fd40308..b666689 100644
--- a/src/include/pc80/mc146818rtc.h
+++ b/src/include/pc80/mc146818rtc.h
@@ -175,7 +175,7 @@ void rtc_check_update_cmos_date(u8 has_century);
 #if CONFIG_USE_OPTION_TABLE
 enum cb_err set_option(const char *name, void *val);
 enum cb_err get_option(void *dest, const char *name);
-unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def);
+unsigned read_option(const char *name, unsigned def);
 #else
 static inline enum cb_err set_option(const char *name __attribute__((unused)),
    			     void *val __attribute__((unused)))
@@ -183,12 +183,11 @@ static inline enum cb_err set_option(const char *name __attribute__((unused)),
 static inline enum cb_err get_option(void *dest __attribute__((unused)),
    			     const char *name __attribute__((unused)))
    			{ return CB_CMOS_OTABLE_DISABLED; }
-#define read_option_lowlevel(start, size, def) def
+#define read_option(name, def) def
 #endif
 #else
 #include <drivers/pc80/mc146818rtc_early.c>
 #endif
-#define read_option(name, default) read_option_lowlevel(CMOS_VSTART_ ##name, CMOS_VLEN_ ##name, (default))

#if CONFIG_CMOS_POST
 #if CONFIG_USE_OPTION_TABLE
diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c
index aa18d2a..0379783 100644
--- a/src/lib/uart8250.c
+++ b/src/lib/uart8250.c
@@ -23,10 +23,6 @@
 #include <pc80/mc146818rtc.h>
 #include <trace.h>

-#if CONFIG_USE_OPTION_TABLE
-#include "option_table.h"
-#endif
-
 /* Should support 8250, 16450, 16550, 16550A type UARTs */

/* Expected character delay at 1200bps is 9ms for a working UART
@@ -119,7 +115,7 @@ void uart_init(void)
    static const unsigned char divisor[8] = { 1, 2, 3, 6, 12, 24, 48, 96 };
    unsigned b_index = 0;
 #if defined(__PRE_RAM__)
-	b_index = read_option(baud_rate, 0);
+	b_index = read_option("baud_rate", 0);
    b_index &= 7;
    div = divisor[b_index];
 #else
diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c
index 1482142..f18e19d 100644
--- a/src/lib/uart8250mem.c
+++ b/src/lib/uart8250mem.c
@@ -21,9 +21,6 @@
 #include <arch/io.h>
 #include <uart8250.h>
 #include <pc80/mc146818rtc.h>
-#if CONFIG_USE_OPTION_TABLE
-#include "option_table.h"
-#endif
 #include <device/device.h>
 #include <delay.h>

@@ -114,7 +111,7 @@ u32 uart_mem_init(void)
    static const unsigned baud[8] = { 115200, 57600, 38400, 19200, 9600, 4800, 2400, 1200 };
    unsigned b_index = 0;
 #if defined(__PRE_RAM__)
-	b_index = read_option(baud_rate, 0);
+	b_index = read_option("baud_rate", 0);
    b_index &= 7;
    uart_baud = baud[b_index];
 #else
diff --git a/src/northbridge/intel/e7520/raminit.c b/src/northbridge/intel/e7520/raminit.c
index 55be449..c4887e7 100644
--- a/src/northbridge/intel/e7520/raminit.c
+++ b/src/northbridge/intel/e7520/raminit.c
@@ -23,9 +23,6 @@
 #include "raminit.h"
 #include "e7520.h"
 #include <pc80/mc146818rtc.h>
-#if CONFIG_HAVE_OPTION_TABLE
-#include "option_table.h"
-#endif

#define BAR 0x40000000

@@ -617,12 +614,10 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,

}
    ecc = 2;
-#if CONFIG_HAVE_OPTION_TABLE
-	if (read_option(ECC_memory, 1) == 0) {
+	if (read_option("ECC_memory", 1) == 0) {
    	ecc = 0;  /* ECC off in CMOS so disable it */
    	print_debug("ECC off\n");
    } else
-#endif
    {
    	print_debug("ECC on\n");
    }
diff --git a/src/northbridge/intel/e7525/raminit.c b/src/northbridge/intel/e7525/raminit.c
index 11f26ee..cf4a7f1 100644
--- a/src/northbridge/intel/e7525/raminit.c
+++ b/src/northbridge/intel/e7525/raminit.c
@@ -24,9 +24,6 @@
 #include "raminit.h"
 #include "e7525.h"
 #include <pc80/mc146818rtc.h>
-#if CONFIG_HAVE_OPTION_TABLE
-#include "option_table.h"
-#endif

#define BAR 0x40000000

@@ -623,12 +620,10 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,

}
    ecc = 2;
-#if CONFIG_HAVE_OPTION_TABLE
-	if (read_option(ECC_memory, 1) == 0) {
+	if (read_option("ECC_memory", 1) == 0) {
    	ecc = 0;  /* ECC off in CMOS so disable it */
    	print_debug("ECC off\n");
    } else
-#endif
    {
    	print_debug("ECC on\n");
    }