Attention is currently required from: Cliff Huang, Kapil Porwal, Pranava Y N, Subrata Banik.
Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email )
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ......................................................................
Patch Set 40:
(9 comments)
File src/soc/intel/pantherlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83798/comment/8f654e73_0ee6c33f?usp... : PS38, Line 292: config VBT_DATA_SIZE_KB : int : default 9
why we need this ?
Not required, removed.
https://review.coreboot.org/c/coreboot/+/83798/comment/ef1bd274_3d969251?usp... : PS38, Line 314: select VBOOT_X86_RSA_ACCELERATION
please follow the order
Acknowledged
https://review.coreboot.org/c/coreboot/+/83798/comment/1c21d9ab_eb9619d6?usp... : PS38, Line 388:
you still need below configs […]
Sure, added.
File src/soc/intel/pantherlake/pcie_rp.c:
https://review.coreboot.org/c/coreboot/+/83798/comment/3f701e28_5953033e?usp... : PS38, Line 8:
please add `tbt_rp_groups` as mentioned previously
Sure, added in patchset 38.
https://review.coreboot.org/c/coreboot/+/83798/comment/e879cffb_f7c82eee?usp... : PS38, Line 11: #if CONFIG(SOC_INTEL_PANTHERLAKE_U_H) : { .slot = PCI_DEV_SLOT_PCIE_2, .count = 4, .lcap_port_base = 1 }, : #endif : #if CONFIG(SOC_INTEL_PANTHERLAKE_H) : { .slot = PCI_DEV_SLOT_PCIE_2, .count = 2, .lcap_port_base = 1 }, : #endif
Acknowledged
File src/soc/intel/pantherlake/retimer.c:
https://review.coreboot.org/c/coreboot/+/83798/comment/edf751d0_98dd4341?usp... : PS38, Line 16: DEV_PTR(tcss_usb3_port2), : };
don't we have 4 TCSS ports
Ack, added tcss_usb3_port3
https://review.coreboot.org/c/coreboot/+/83798/comment/eb00d6ee_a3d3ce60?usp... : PS38, Line 20: _MAX_TYPE_C_PORTS
why don't you use the macro (MAX_TYPE_C_PORTS) directly coming from TCSS. […]
Ack, added MAX_TYPE_C_PORTS.
File src/soc/intel/pantherlake/spi.c:
https://review.coreboot.org/c/coreboot/+/83798/comment/3972aab3_9c2ed6ef?usp... : PS38, Line 12: case PCI_DEVFN_SPI: : return 0;
this is fast SPI and doesn't belong here.
Ack, removed.
https://review.coreboot.org/c/coreboot/+/83798/comment/57b40c9d_d90ca5ee?usp... : PS38, Line 18: }
please add GSPI index 2 here
Ack, added GSPI2.