Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43917 )
Change subject: mb/protectli/vault_kbl: Relocate devicetree FSP settings ......................................................................
mb/protectli/vault_kbl: Relocate devicetree FSP settings
Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.
Change-Id: Iff63c6ff91bdf040c845c4d28f726410151bbf6b Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/protectli/vault_kbl/devicetree.cb 1 file changed, 86 insertions(+), 76 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/43917/1
diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 5f757e8..86662fb 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -34,26 +34,13 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "1" - register "SataSalpSupport" = "0" - register "SataMode" = "0" - register "EnableAzalia" = "0" register "DspEnable" = "0" register "IoBufferOwnership" = "0" - register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" register "Cio2Enable" = "0" - register "ScsEmmcEnabled" = "0" - register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "0" - register "HeciEnabled" = "1" register "PmTimerDisabled" = "1" register "SaGv" = "SaGv_Enabled" - register "SaImguEnable" = "0" register "IslVrCmd" = "2" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "4" # 4s @@ -128,56 +115,6 @@ # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2"
- # Enable SATA ports 1,2 - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - register "SataPortsEnable[2]" = "0" - register "SataPortsDevSlp[0]" = "0" - register "SataPortsDevSlp[1]" = "0" - - # Enable Root ports. 1-6 for LAN and Root Port 9 - register "PcieRpEnable[0]" = "1" - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[2]" = "1" - register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" - register "PcieRpEnable[8]" = "1" # mPCIe WiFi - - # Enable Advanced Error Reporting for RP 1-6, 9 - register "PcieRpAdvancedErrorReporting[0]" = "1" - register "PcieRpAdvancedErrorReporting[1]" = "1" - register "PcieRpAdvancedErrorReporting[2]" = "1" - register "PcieRpAdvancedErrorReporting[3]" = "1" - register "PcieRpAdvancedErrorReporting[4]" = "1" - register "PcieRpAdvancedErrorReporting[5]" = "1" - register "PcieRpAdvancedErrorReporting[8]" = "1" - - # Enable Latency Tolerance Reporting Mechanism RP 1-6, 9 - register "PcieRpLtrEnable[0]" = "1" - register "PcieRpLtrEnable[1]" = "1" - register "PcieRpLtrEnable[2]" = "1" - register "PcieRpLtrEnable[3]" = "1" - register "PcieRpLtrEnable[4]" = "1" - register "PcieRpLtrEnable[5]" = "1" - register "PcieRpLtrEnable[8]" = "1" - - # Enable RP 9 CLKREQ# support - register "PcieRpClkReqSupport[8]" = "1" - # RP 9 uses CLKREQ0# - register "PcieRpClkReqNumber[8]" = "0" - - # Clocks 0-5 for RP 1-6 - register "PcieRpClkSrcNumber[0]" = "0" - register "PcieRpClkSrcNumber[1]" = "1" - register "PcieRpClkSrcNumber[2]" = "2" - register "PcieRpClkSrcNumber[3]" = "3" - register "PcieRpClkSrcNumber[4]" = "4" - register "PcieRpClkSrcNumber[5]" = "5" - # RP 9 shares CLKSRC5# with RP 6 - register "PcieRpClkSrcNumber[8]" = "5" - - # USB 2.0 enable ports 1-8, disable ports 9-12 register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # TYPE-A Port @@ -225,6 +162,13 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + + # SA thermal device disabled + register "Device4Enable" = "0" + + # IMGU disabled + register "SaImguEnable" = "0" + device pci 08.0 off end # Gaussian Mixture Model device pci 13.0 off end # Integrated Sensor Hub device pci 14.0 on end # USB xHCI @@ -235,24 +179,77 @@ device pci 15.1 off end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 + device pci 16.0 on # Management Engine Interface 1 + register "HeciEnabled" = "1" + end device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 - device pci 17.0 on end # SATA + device pci 17.0 on # SATA + register "EnableSata" = "1" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + + # Enable SATA ports 1, 2 + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 1, \ + [2] = 0, \ + }" + register "SataPortsDevSlp" = "{ \ + [0] = 0, \ + [1] = 0, \ + }" + end device pci 19.0 off end # UART #2 device pci 19.1 off end # I2C #5 device pci 19.2 off end # I2C #4 - device pci 1c.0 on end # PCI Express Port 1 - device pci 1c.1 on end # PCI Express Port 2 - device pci 1c.2 on end # PCI Express Port 3 - device pci 1c.3 on end # PCI Express Port 4 - device pci 1c.4 on end # PCI Express Port 5 - device pci 1c.5 on end # PCI Express Port 6 + device pci 1c.0 on # PCI Express Port 1 - LAN + register "PcieRpEnable[0]" = "1" + register "PcieRpAdvancedErrorReporting[0]" = "1" + register "PcieRpLtrEnable[0]" = "1" + register "PcieRpClkSrcNumber[0]" = "0" + end + device pci 1c.1 on # PCI Express Port 2 - LAN + register "PcieRpEnable[1]" = "1" + register "PcieRpAdvancedErrorReporting[1]" = "1" + register "PcieRpLtrEnable[1]" = "1" + register "PcieRpClkSrcNumber[1]" = "1" + end + device pci 1c.2 on # PCI Express Port 3 - LAN + register "PcieRpEnable[2]" = "1" + register "PcieRpAdvancedErrorReporting[2]" = "1" + register "PcieRpLtrEnable[2]" = "1" + register "PcieRpClkSrcNumber[2]" = "2" + end + device pci 1c.3 on # PCI Express Port 4 - LAN + register "PcieRpEnable[3]" = "1" + register "PcieRpAdvancedErrorReporting[3]" = "1" + register "PcieRpLtrEnable[3]" = "1" + register "PcieRpClkSrcNumber[3]" = "3" + end + device pci 1c.4 on # PCI Express Port 5 - LAN + register "PcieRpEnable[4]" = "1" + register "PcieRpAdvancedErrorReporting[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieRpClkSrcNumber[4]" = "4" + end + device pci 1c.5 on # PCI Express Port 6 - LAN + register "PcieRpEnable[5]" = "1" + register "PcieRpAdvancedErrorReporting[5]" = "1" + register "PcieRpLtrEnable[5]" = "1" + register "PcieRpClkSrcNumber[5]" = "5" + end device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 device pci 1d.0 on # PCI Express Port 9 - WiFi + register "PcieRpEnable[8]" = "1" + register "PcieRpAdvancedErrorReporting[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "0" + register "PcieRpClkSrcNumber[8]" = "5" # shared w/ RP 6 smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO" "SlotLengthShort" "WIFI1" "SlotDataBusWidth1X" @@ -264,9 +261,14 @@ device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 device pci 1e.3 off end # GSPI #1 - device pci 1e.4 off end # eMMC + device pci 1e.4 off # eMMC + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + end device pci 1e.5 off end # SDIO - device pci 1e.6 off end # SDCard + device pci 1e.6 off # SDCard + register "ScsSdCardEnabled" = "0" + end device pci 1f.0 on chip superio/ite/it8772f register "peci_tmpin" = "3" @@ -291,10 +293,18 @@ end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 off end # Intel HDA - device pci 1f.4 on end # SMBus + device pci 1f.3 off # Intel HDA + register "EnableAzalia" = "0" + end + device pci 1f.4 on # SMBus + register "SmbusEnable" = "1" + end device pci 1f.5 off end # PCH SPI - device pci 1f.6 off end # GbE + device pci 1f.6 off # GbE + register "EnableLan" = "0" + end + + register "EnableTraceHub" = "0" end chip drivers/crb device mmio 0xfed40000 on end
Hello build bot (Jenkins), Michał Żygowski, Piotr Król,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43917
to look at the new patch set (#2).
Change subject: mb/protectli/vault_kbl: Relocate devicetree settings ......................................................................
mb/protectli/vault_kbl: Relocate devicetree settings
Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.
Change-Id: Iff63c6ff91bdf040c845c4d28f726410151bbf6b Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/protectli/vault_kbl/devicetree.cb 1 file changed, 86 insertions(+), 76 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/43917/2
Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/43917 )
Change subject: mb/protectli/vault_kbl: Relocate devicetree settings ......................................................................
Abandoned
-
Angel Pons (Code Review)