Aaron Durbin (adurbin@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9259
-gerrit
commit 969087a98f5b11bc7cf0efcc2e0115958ec8ba2c Author: huang lin hl@rock-chips.com Date: Fri Oct 10 23:26:21 2014 -0700
rk3288: guarantee i2c low period more than 1.3us
change i2c clock low period and high period proportion to 7:3 guarantee the low period more than 1.3us
BUG=None TEST=Boot on veyron_pinky rev2,check the i2c clock frequency
Original-Change-Id: I235e9e3ff54ab3b9cabad36bab58a8409f7005a0 Original-Signed-off-by: huang lin hl@rock-chips.com Original-Reviewed-on: https://chromium-review.googlesource.com/223002 Original-Reviewed-by: Julius Werner jwerner@chromium.org
(cherry picked from commit 57a5d90d394086483e0dcdd6279678658d07d842) Signed-off-by: Aaron Durbin adurbin@chromium.org
Change-Id: I6b0c9dfa540354f6463ed90c9f3f9503a4d5749e --- src/soc/rockchip/rk3288/i2c.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/soc/rockchip/rk3288/i2c.c b/src/soc/rockchip/rk3288/i2c.c index 142ec4a..eb480a7 100644 --- a/src/soc/rockchip/rk3288/i2c.c +++ b/src/soc/rockchip/rk3288/i2c.c @@ -284,7 +284,7 @@ void i2c_init(unsigned int bus, unsigned int hz) unsigned int clk_div; unsigned int divl; unsigned int divh; - unsigned int i2c_src_clk; + unsigned int i2c_src_clk = 0; struct rk3288_i2c_regs *regs = i2c_bus[bus];
/*i2c0,i2c2 src clk from pd_bus_pclk @@ -308,9 +308,9 @@ void i2c_init(unsigned int bus, unsigned int hz) /*SCL Divisor = 8*(CLKDIVL + 1 + CLKDIVH + 1) SCL = PCLK/ SCLK Divisor */ - clk_div = div_round_up(i2c_src_clk, hz * 8) - 2; - divh = clk_div / 2; - divl = ALIGN_UP(clk_div, 2) / 2; + clk_div = div_round_up(i2c_src_clk, hz * 8); + divh = clk_div * 3 / 7 - 1; + divl = clk_div - divh - 2; assert((divh < 65536) && (divl < 65536)); writel((divh << 16) | (divl << 0), ®s->i2c_clkdiv); }