Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47578 )
Change subject: [WIP] nb/intel/sandybridge: Simplify rcven coarse stats ......................................................................
[WIP] nb/intel/sandybridge: Simplify rcven coarse stats
Change-Id: Ief17dbd7633b010f2775bf4b5ed9151a139540b2 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 101 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/47578/1
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index f20181e..03ae877 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -909,6 +909,11 @@ LANEBASE_ECC };
+static u32 gdcr_read32(const int offset, const int lane) +{ + return MCHBAR32(lane_base[lane] + offset); +} + void program_timings(ramctr_timing *ctrl, int channel) { u32 reg_roundtrip_latency, reg_pi_code, reg_logic_delay, reg_io_latency; @@ -1115,26 +1120,112 @@ return ret; }
+static void print_raw_statistics(ramctr_timing *ctrl, u32 statistics[NUM_LANES][4], int sz) +{ + printk(BIOS_ERR, "Delay\t01234567%c\n", ctrl->lanes == NUM_LANES ? '8' : ' '); + + for (int j = 0; j < sz; j++) { + for (int i = 0; i < 32; i++) { + printk(BIOS_ERR, "% 5d\t", i + j * 32); + + int lane; + FOR_ALL_LANES { + const bool pass = !!(statistics[lane][j] & 1 << i); + printk(BIOS_ERR, "%c", pass ? '#' : '.'); + } + printk(BIOS_ERR, "\n"); + } + } +} + +static struct run get_passing_region(u32 *statistics, int sz) +{ + /* Initialize all variables depending on whether the first point passed or not */ + const int init_value = statistics[0] & 1 ? 0 : -1; + + int initial_lower = init_value; + int initial_upper = init_value; + int current_lower = init_value; + int current_upper = init_value; + int largest_lower = init_value; + int largest_upper = init_value; + + for (int j = 0; j < sz; j++) { + for (int i = 0; i < 32; i++) { + + const int idx = i + j * 32; + + if (idx == 0) + continue; + + if (!(statistics[j] & 1 << i)) + continue; + + /* Update initial region upper limit */ + if (initial_upper == idx - 1) + initial_upper = idx; + + /* If this pass is not contiguous, start a new pass region */ + if (current_upper != idx - 1) + current_lower = idx; + + /* Update current region upper limit */ + current_upper = idx; + + /* Update largest variables */ + if (current_upper - current_lower > largest_upper - largest_lower) { + largest_lower = current_lower; + largest_upper = current_upper; + } + } + } + + printk(BIOS_ERR, "\nStats: IL: %d, IU: %d, CL: %d, CU: %d, LL: %d, LU: %d\n", + initial_lower, initial_upper, + current_lower, current_upper, + largest_upper, largest_upper); + + printk(BIOS_ERR, "\n"); + + return (struct run) { + .middle = (largest_upper + largest_lower) / 2, + .end = largest_upper, + .start = largest_lower, + .length = largest_upper - largest_lower, + }; +} + +static u32 get_stats(int channel, int lane, int idx) +{ + return gdcr_read32(GDCRTRAININGRESULT(channel, idx), lane); +} + static void discover_timA_coarse(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) { int timA; - int statistics[NUM_LANES][128]; + u32 statistics[NUM_LANES][4]; int lane;
- for (timA = 0; timA < 128; timA++) { - FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].timA = timA; + for (u32 logic_delay = 0; logic_delay < 2; logic_delay++) { + for (timA = 0; timA < 64; timA++) { + FOR_ALL_LANES { + ctrl->timings[channel][slotrank].lanes[lane].timA = + timA + logic_delay * 64; + } + program_timings(ctrl, channel); + + test_timA(ctrl, channel, slotrank); } - program_timings(ctrl, channel); - - test_timA(ctrl, channel, slotrank); - FOR_ALL_LANES { - statistics[lane][timA] = !does_lane_work(ctrl, channel, slotrank, lane); + statistics[lane][logic_delay * 2 + 0] = get_stats(channel, lane, 0); + statistics[lane][logic_delay * 2 + 1] = get_stats(channel, lane, 1); } } + printk(BIOS_ERR, "Channel %d results:\n", channel); + print_raw_statistics(ctrl, statistics, 4); + FOR_ALL_LANES { - struct run rn = get_longest_zero_run(statistics[lane], 128); + struct run rn = get_passing_region(statistics[lane], 4); ctrl->timings[channel][slotrank].lanes[lane].timA = rn.middle; upperA[lane] = rn.end; if (upperA[lane] < rn.middle)
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47578
to look at the new patch set (#2).
Change subject: [WIP] nb/intel/sandybridge: Simplify rcven coarse stats ......................................................................
[WIP] nb/intel/sandybridge: Simplify rcven coarse stats
Tested on Asus P8H61-M PRO, still boots.
Change-Id: Ief17dbd7633b010f2775bf4b5ed9151a139540b2 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 116 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/47578/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47578 )
Change subject: [WIP] nb/intel/sandybridge: Simplify rcven coarse stats ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47578/3/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_common.c:
https://review.coreboot.org/c/coreboot/+/47578/3/src/northbridge/intel/sandy... PS3, Line 1194: if (initial_lower == 0 && initial_upper != current_upper) { braces {} are not necessary for single statement blocks
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47578 )
Change subject: [WIP] nb/intel/sandybridge: Simplify rcven coarse stats ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47578/4/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_common.c:
https://review.coreboot.org/c/coreboot/+/47578/4/src/northbridge/intel/sandy... PS4, Line 1194: if (initial_lower == 0 && initial_upper != current_upper) { braces {} are not necessary for single statement blocks
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47578 )
Change subject: [WIP] nb/intel/sandybridge: Simplify rcven coarse stats ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47578/5/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_common.c:
https://review.coreboot.org/c/coreboot/+/47578/5/src/northbridge/intel/sandy... PS5, Line 1194: if (initial_lower == 0 && initial_upper != current_upper) { braces {} are not necessary for single statement blocks
-
Angel Pons (Code Review) -
build bot (Jenkins) (Code Review)