Change in coreboot[master]: soc/intel/jasperlake: CNVi: Enable fewer wakeups to reduce SoC power ...

[Jamie Chen (Code Review)]

Attention is currently required from: Tim Wawrzynczak, Karthik Ramasubramanian.
Jamie Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63675 )

Change subject: soc/intel/jasperlake: CNVi: Enable fewer wakeups to reduce SoC power consumption
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Patch Set 5:

(2 comments)

File src/soc/intel/jasperlake/chip.h:

https://review.coreboot.org/c/coreboot/+/63675/comment/c544e271_dcb11447 
PS5, Line 428:  * Setting this on a system that supports S0i3 (set xtalsdqdis [Bit 22] in
             : 	 * cppmvric1 register to 0) will break CNVI timing.
> Should we have to assert xtalsdqdis bit is not set when this bit is set?

The xtalsdqdis bit can be set or clear by ASL code or OS code. That's why I add comment here to warning developer instead of adding statement to check if xtalsdqis bit is 0.

File src/soc/intel/jasperlake/finalize.c:

https://review.coreboot.org/c/coreboot/+/63675/comment/38113da8_fab4a710 
PS5, Line 63: 		if (config->cnvi_reduce_s0ix_pwr_usage) {
> Also should we have to ensure that CNVI device is enabled in the devicetree. […]

This is only for system with CNVi module to work around and keeping this enabled will not impact the system with discrete WIFI.