[M] Change in coreboot[master]: mb/google/brya/gaelin: Change DDR4 from interleave to non-interleave - coreboot-gerrit

25 Oct 2022


      Attention is currently required from: Derek Huang, Tim Wawrzynczak, Zhuohao Lee.
Raymond Chung has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68806 )
Change subject: mb/google/brya/gaelin: Change DDR4 from interleave to non-interleave
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Patch Set 2: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68806/comment/7dbd5da0_15bb62e9 
PS1, Line 9: The brask DDR4 is set to interleave, due to the limited number of gaelin PCB layers and the traces need to be smooth, we will use non-interleave for gaelin DDR4.
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Please fix.
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I34413343e3f7c283f49fbbdd277d9da39c09f9f8
Gerrit-Change-Number: 68806
Gerrit-PatchSet: 2
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