John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69565 )
Change subject: mb/google/skyrim/var/frostflow: Set DPTC Electrical Parameters ......................................................................
mb/google/skyrim/var/frostflow: Set DPTC Electrical Parameters
Set DPTC Electrical Parameters form AMD DevHub document #57316.
"system_configuration" = "4" "slow_ppt_limit_mW" = "15000" "fast_ppt_limit_mW" = "22000" "stapm_time_constant_s" = "200" "thermctl_limit_degreeC" = "100" "vrm_current_limit_mA" = "28000" "vrm_maximum_current_limit_mA" = "50000" "vrm_soc_current_limit_mA" = "10000"
BRANCH=none BUG=b:257187831 TEST=emerge-skyrim coreboot
Signed-off-by: John Su john_su@compal.corp-partner.google.com Change-Id: I15a69df1436aba05bc19eaffd79394e5ca9bdb3a --- M src/mainboard/google/skyrim/variants/frostflow/overridetree.cb 1 file changed, 37 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/69565/1
diff --git a/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb b/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb index a3858c8..5581d40 100644 --- a/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/frostflow/overridetree.cb @@ -1,6 +1,18 @@ # SPDX-License-Identifier: GPL-2.0-or-later
chip soc/amd/mendocino + # System config index + register "system_configuration" = "4" + + # Set DPTC Electrical Parameters + register "slow_ppt_limit_mW" = "15000" + register "fast_ppt_limit_mW" = "22000" + register "stapm_time_constant_s" = "200" + register "thermctl_limit_degreeC" = "100" + register "vrm_current_limit_mA" = "28000" + register "vrm_maximum_current_limit_mA" = "50000" + register "vrm_soc_current_limit_mA" = "10000" + device domain 0 on device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref xhci_1 on # XHCI1 controller