[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
Attention is currently required from: Ashish Kumar Mishra, Cliff Huang, Dinesh Gehlot, Elyes Haouas, Eran Mitrani, Felix Singer, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Ravishankar Sarawadi, Saurabh Mishra, Subrata Banik, Tarun.
Wonkyu Kim has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83354?usp=email )
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock ......................................................................
Patch Set 61:
(10 comments)
File src/soc/intel/pantherlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83354/comment/a18eb875_4ccf6d26?usp... : PS36, Line 53: 22
I guess we need to revisit this. […]
Yes, it should be 4+8+4=16 for H SKU.
File src/soc/intel/pantherlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83354/comment/491f98e0_0eb8ff0c?usp... : PS48, Line 95: config P2SB_2_PCR_BASE_ADDRESS Can we use similar definition as PCR2_BASE_ADDRESS?
File src/soc/intel/pantherlake/bootblock/pcd.c:
https://review.coreboot.org/c/coreboot/+/83354/comment/25b7a702_ebdd6947?usp... : PS47, Line 27: #define PCR_PSFX_TO_SHDW_BAR0 0 Remove unused definitions #define PCR_PSFX_TO_SHDW_BAR0 0 #define PCR_PSFX_TO_SHDW_BAR1 0x4 #define PCR_PSFX_TO_SHDW_BAR2 0x8 #define PCR_PSFX_TO_SHDW_BAR3 0xC
https://review.coreboot.org/c/coreboot/+/83354/comment/eaf4a644_6b79b694?usp... : PS47, Line 35: #define PCR_DMI_ACPIBA 0x27B4 Remove unused definitions #define PCR_DMI_ACPIBA 0x27B4 #define PCR_DMI_ACPIBDID 0x27B8 #define PCR_DMI_PMBASEA 0x27AC #define PCR_DMI_PMBASEC 0x27B0
File src/soc/intel/pantherlake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/83354/comment/387fed74_02bd2023?usp... : PS48, Line 20: 2000000 Can we use MiB instead of direct hex value? And Can we also update all size value by using KiB and MiB for readablity?
https://review.coreboot.org/c/coreboot/+/83354/comment/a970f517_3e25f3da?usp... : PS48, Line 72: #define P2SB2_BAR CONFIG_P2SB_2_PCR_BASE_ADDRESS Can we use like PCR2_BASE_ADDRESS?
File src/soc/intel/pantherlake/include/soc/pcr_ids.h:
https://review.coreboot.org/c/coreboot/+/83354/comment/fac8af6a_5e6aa795?usp... : PS48, Line 14: #define PID_PSF15 0xB4 For PID_PSFn, can you add only used define? It looks only PID_PSF8 is used for Pantherlalke.
https://review.coreboot.org/c/coreboot/+/83354/comment/ecc8983f_55b33ad4?usp... : PS48, Line 26: #define PID_DMI 0x2F This is dummy value. Can you check if we remove this cause build error? If this cause build error, can you add comments this is dummy value which we don't use?
https://review.coreboot.org/c/coreboot/+/83354/comment/dbbf9bf5_0ae5aba4?usp... : PS48, Line 27: #define PID_NPK 0x8C PID_NPK is used?
https://review.coreboot.org/c/coreboot/+/83354/comment/abc8e530_7b95bdfc?usp... : PS48, Line 28: #define PID_XHCI 0x3A Is this value is correct? according to BIOS reference code USB Host controller P2SB id is 0x09.
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Wonkyu Kim (Code Review)