Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Elyes Haouas, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Wonkyu Kim.
Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83789?usp=email )
Change subject: soc/intel/ptl: Add GPIOs for Panther Lake SOC
......................................................................
Patch Set 43:
(1 comment)
File src/soc/intel/pantherlake/gpio.c:
https://review.coreboot.org/c/coreboot/+/83789/comment/5f6865ba_b1308fbf?usp... :
PS17, Line 54: .port = PID_GPIOCOM0,
sorry. my bad. typo Subrata:)
Sorry, I'm unable to follow what you mean by PTL requires PID numbers as word size compared to ADL-MTL. I could see all GPIO PIDs for PTL are byte width and not word width.
```
#define PID_GPIOCOM0 0x59
#define PID_GPIOCOM1 0x5A
#define PID_GPIOCOM3 0x5B
#define PID_GPIOCOM4 0x5C
#define PID_GPIOCOM5 0x5D
```
So far we are using cpu_port PID which is same as GPIO comm Port ID, for example: in Alder Lake, the port id for COMM_0 and cpu_port PID for COMM_0 are same. I have seen the same logic even in MTL as well.
```
[COMM_0] = { /* GPP B, T, A */
.port = PID_GPIOCOM0,
.cpu_port = PID_CPU_GPIOCOM0,
```
Are you saying, in PTL, cpu_port PID and port ID won't point to same PID value, where port id is still byte width but cpu_port PID is word width ?
Coming to how are we using cpu_port PIDs? we are using cpu_port PIDs for programming the AUX PAD configuration. This is not specific TCSS or any IP. This is still points to the GPIO PIN/PAD hence, we are relying on the GPIO community PID for cpu_port while calling calc_bias_ctrl_reg_value(). Example below, we would need to know the cpu_port PID for USB-C0 AUX pins.
```
register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
```
I'm not very clear what you mean by " It turns out that the port id is 16-bit in PTL.".
If the cpu_port IDs for GPIO banks would be word width then I suggest doing refactoring of the common code by adding a new Kconfig (SOC_INTEL_COMMON_BLOCK_GPIO_CPU_PORT_16BITS) to update the common code data structure. But before that, please help me to understand the delta that PTL is bringing.
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