New subject: Change in ...coreboot[master]: inteltool: add coffeelake support

19 Feb 2019

Thomas Heijligen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31501
Change subject: inteltool: coffeelake support
......................................................................
inteltool: coffeelake support
Change-Id: I9f3b3108f5672b557610fa7d8fbd5c199af8d353
Signed-off-by: Thomas Heijligen thomas.heijligen@secunet.com
---
M util/inteltool/gpio.c
M util/inteltool/gpio_groups.c
M util/inteltool/pcr.c
3 files changed, 495 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/31501/1

diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c
index dd09214..2f51a44 100644
--- a/util/inteltool/gpio.c
+++ b/util/inteltool/gpio.c
@@ -1033,6 +1033,16 @@
    case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE:
    case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM:
    case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM:
+	case PCI_DEVICE_ID_INTEL_H310:
+	case PCI_DEVICE_ID_INTEL_H370:
+	case PCI_DEVICE_ID_INTEL_Z390:
+	case PCI_DEVICE_ID_INTEL_Q370:
+	case PCI_DEVICE_ID_INTEL_B360:
+	case PCI_DEVICE_ID_INTEL_C246:
+	case PCI_DEVICE_ID_INTEL_C242:
+	case PCI_DEVICE_ID_INTEL_QM370:
+	case PCI_DEVICE_ID_INTEL_HM370:
+	case PCI_DEVICE_ID_INTEL_CM246:
    	print_gpio_groups(sb);
    	return 0;
    case PCI_DEVICE_ID_INTEL_82371XX:
diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c
index 53a8eb9..c50917e 100644
--- a/util/inteltool/gpio_groups.c
+++ b/util/inteltool/gpio_groups.c
@@ -841,6 +841,456 @@
    &denverton_community_north, &denverton_community_south,
 };
+
+
+// heijligen
+static const char *const coffeelake_group_a_names[] = {
+	"GPP_A0",	"RCIN#",		"n/a",			"ESPI_ALERT1#",		"n/a",
+	"GPP_A1",	"LAD0",			"n/a",			"ESPI_IO0",		"n/a",
+	"GPP_A2",	"LAD1",			"n/a",			"ESPI_IO1",		"n/a",
+	"GPP_A3",	"LAD2",			"n/a",			"ESPI_IO2",		"n/a",
+	"GPP_A4",	"LAD3",			"n/a",			"ESPI_IO3",		"n/a",
+	"GPP_A5",	"LFRAME#",		"n/a",			"ESPI_CS0#",		"n/a",
+	"GPP_A6",	"SERIRQ",		"n/a",			"ESPI_CS1#",		"n/a",
+	"GPP_A7",	"PIRQA#",		"n/a",			"ESPI_ALERT0#",		"n/a",
+	"GPP_A8",	"CLKRUN#",		"n/a",			"n/a",			"n/a",
+	"GPP_A9",	"CLKOUT_LPC0",		"n/a",			"ESPI_CLK",		"n/a",
+	"GPP_A10",	"CLKOUT_LPC1",		"n/a",			"n/a",			"n/a",
+	"GPP_A11",	"PME#",			"SD_VDD_PWR_EN#",	"n/a",			"n/a",
+	"GPP_A12",	"BM_BUSY#",		"ISH_GP6",		"SX_EXIT_HOLDOFF#",	"n/a",
+	"GPP_A13",	"SUSWARN#/SUSPWRDNACK",	"n/a",			"n/a",			"n/a",
+	"GPP_A14",	"SUS_STAT#",		"n/a",			"ESPI_RESET#",		"n/a",
+	"GPP_A15",	"SUSACK#",		"n/a",			"n/a",			"n/a",
+	"GPP_A16",	"CLKOUT_48",		"n/a",			"n/a",			"n/a",
+	"GPP_A17",	"SD_VDD1_PWR_EN#",	"ISH_GP7",		"n/a",			"n/a",
+	"GPP_A18",	"ISH_GP0",		"n/a",			"n/a",			"n/a",
+	"GPP_A19",	"ISH_GP1",		"n/a",			"n/a",			"n/a",
+	"GPP_A20",	"ISH_GP2",		"n/a",			"n/a",			"n/a",
+	"GPP_A21",	"ISH_GP3",		"n/a",			"n/a",			"n/a",
+	"GPP_A22",	"ISH_GP4",		"n/a",			"n/a",			"n/a",
+	"GPP_A23",	"ISH_GP5",		"n/a",			"n/a",			"n/a",
+};
+
+static const struct gpio_group coffeelake_group_a = {
+	.display	= "------- GPIO Group GPP_A -------",
+	.pad_count	= ARRAY_SIZE(coffeelake_group_a_names) / 5,
+	.func_count	= 5,
+	.pad_names	= coffeelake_group_a_names,
+};
+
+static const char *const coffeelake_group_b_names[] = {
+	"GPP_B0",	"GSPI0_CS1#",	"n/a",		"n/a",	"n/a",
+	"GPP_B1",	"GSPI1_CS1#",	"TIME_SYNC1",	"n/a",	"n/a",
+	"GPP_B2",	"VRALRERT#",	"n/a",		"n/a",	"n/a",
+	"GPP_B3",	"CPU_GP2",	"n/a",		"n/a",	"n/a",
+	"GPP_B4",	"CPU_GP3",	"n/a",		"n/a",	"n/a",
+	"GPP_B5",	"SRCCLKREQ0#",	"n/a",		"n/a",	"n/a",
+	"GPP_B6",	"SRCCLKREQ1#",	"n/a",		"n/a",	"n/a",
+	"GPP_B7",	"SRCCLKREQ2#",	"n/a",		"n/a",	"n/a",
+	"GPP_B8",	"SRCCLKREQ3#",	"n/a",		"n/a",	"n/a",
+	"GPP_B9",	"SRCCLKREQ4#",	"n/a",		"n/a",	"n/a",
+	"GPP_B10",	"SRCCLKREQ5#",	"n/a",		"n/a",	"n/a",
+	"GPP_B11",	"I2S_MCLK",	"n/a",		"n/a",	"n/a",
+	"GPP_B12",	"SLP_S0#",	"n/a",		"n/a",	"n/a",
+	"GPP_B13",	"PLTRST#",	"n/a",		"n/a",	"n/a",
+	"GPP_B14",	"SPKR",		"n/a",		"n/a",	"n/a",
+	"GPP_B15",	"GSPI0_CS0#",	"n/a",		"n/a",	"n/a",
+	"GPP_B16",	"GSPI0_CLK",	"n/a",		"n/a",	"n/a",
+	"GPP_B17",	"GSPI0_MISO",	"n/a",		"n/a",	"n/a",
+	"GPP_B18",	"GSPI0_MOSI",	"n/a",		"n/a",	"n/a",
+	"GPP_B19",	"GSPI1_CS0#",	"n/a",		"n/a",	"n/a",
+	"GPP_B20",	"GSPI1_CLK",	"n/a",		"n/a",	"n/a",
+	"GPP_B21",	"GSPI1_MISO",	"n/a",		"n/a",	"n/a",
+	"GPP_B22",	"GSPI1_MOSI",	"n/a",		"n/a",	"n/a",
+	"GPP_B23",	"SML1ALERT#",	"PCHHOT#",	"n/a",	"n/a",
+};
+
+static const struct gpio_group coffeelake_group_b = {
+	.display	= "------- GPIO Group GPP_B -------",
+	.pad_count	= ARRAY_SIZE(coffeelake_group_b_names) / 5,
+	.func_count	= 5,
+	.pad_names	= coffeelake_group_b_names,
+};
+
+
+static const char *const coffeelake_group_c_names[] = {
+	"GPP_C0",	"SMBCLK",	"n/a",			"n/a",	"n/a",
+	"GPP_C1",	"SMBDATA",	"n/a",			"n/a",	"n/a",
+	"GPP_C2",	"SMBALERT#",	"n/a",			"n/a",	"n/a",
+	"GPP_C3",	"SML0CLK",	"n/a",			"n/a",	"n/a",
+	"GPP_C4",	"SML0DATA",	"n/a",			"n/a",	"n/a",
+	"GPP_C5",	"SML0ALERT#",	"n/a",			"n/a",	"n/a",
+	"GPP_C6",	"SML1CLK",	"n/a",			"n/a",	"n/a",
+	"GPP_C7",	"SML1DATA",	"n/a",			"n/a",	"n/a",
+	"GPP_C8",	"UART0A_RXD",	"n/a",			"n/a",	"n/a",
+	"GPP_C9",	"UART0A_TXD",	"n/a",			"n/a",	"n/a",
+	"GPP_C10",	"UART0A_RTS#",	"n/a",			"n/a",	"n/a",
+	"GPP_C11",	"UART0A_CTS#",	"n/a",			"n/a",	"n/a",
+	"GPP_C12",	"UART1_RXD",	"ISH_UART1_RXD",	"n/a",	"n/a",
+	"GPP_C13",	"UART1_TXD",	"ISH_UART1_TXD",	"n/a",	"n/a",
+	"GPP_C14",	"UART1_RTS#",	"ISH_UART1_RTS#",	"n/a",	"n/a",
+	"GPP_C15",	"UART1_CTS#",	"ISH_UART1_CTS#",	"n/a",	"n/a",
+	"GPP_C16",	"I2C0_SDA",	"n/a",			"n/a",	"n/a",
+	"GPP_C17",	"I2C0_SCL",	"n/a",			"n/a",	"n/a",
+	"GPP_C18",	"I2C1_SDA",	"n/a",			"n/a",	"n/a",
+	"GPP_C19",	"I2C1_SCL",	"n/a",			"n/a",	"n/a",
+	"GPP_C20",	"UART2_RXD",	"n/a",			"n/a",	"n/a",
+	"GPP_C21",	"UART2_TXD",	"n/a",			"n/a",	"n/a",
+	"GPP_C22",	"UART2_RTS#",	"n/a",			"n/a",	"n/a",
+	"GPP_C23",	"UART2_CTS#",	"n/a",			"n/a",	"n/a",
+};
+
+static const struct gpio_group coffeelake_group_c = {
+	.display	= "------- GPIO Group GPP_C -------",
+	.pad_count	= ARRAY_SIZE(coffeelake_group_c_names) / 5,
+	.func_count	= 5,
+	.pad_names	= coffeelake_group_c_names,
+};
+
+
+static const char *const coffeelake_group_d_names[] = {
+	"GPP_D0",	"SPI1_CS#",		"n/a",		"SBK0",			"BK0",
+	"GPP_D1",	"SPI1_CLK",		"n/a",		"SBK1",			"BK1",
+	"GPP_D2",	"SPI1_MISO",		"n/a",		"SBK2",			"BK2",
+	"GPP_D3",	"SPI2_MOSI",		"n/a",		"SBK3",			"BK3",
+	"GPP_D4",	"ISH_I2C2SDA",		"I2C3_SDA",	"SBK4",			"BK4"
+	"GPP_D5",	"I2S2_SFRM",		"n/a",		"CNV_RF_RESET#",	"n/a",
+	"GPP_D6",	"I2S2_TXD",		"n/a",		"modem_CLKREQ",		"n/a",
+	"GPP_D7",	"I2S2_RXD",		"n/a",		"n/a",			"n/a",
+	"GPP_D8",	"I2S2_SCLK",		"n/a",		"n/a",			"n/a",
+	"GPP_D9",	"ISH_SPI_CS#",		"n/a",		"GSPI2_CS0#",		"n/a",
+	"GPP_D10",	"ISH_SPI_CLK",		"n/a",		"GSPI2_CLK",		"n/a",
+	"GPP_D11",	"ISH_SPI_MISO",		"GP_BSSB_CLK",	"GSPI2_MISO",		"n/a",
+	"GPP_D12",	"ISH_SPI_MOSI",		"GP_BSSB_DI",	"GSPI2_MOSI",		"n/a",
+	"GPP_D13",	"ISH_UART0_RXD",	"n/a",		"I2C2_SDA",		"n/a",
+	"GPP_D14",	"ISH_UART0_TXD",	"n/a",		"I2C2_SCL",		"n/a",
+	"GPP_D15",	"ISH_UART0_RTS#",	"GSPI_CS1#",	"n/a",			"CNV_WFEN",
+	"GPP_D16",	"ISH_UART0_CTS#",	"n/a",		"n/a",			"CNV_WCEN",
+	"GPP_D17",	"DMIC_CLK1",		"SNDW3_CLK",	"n/a",			"n/a",
+	"GPP_D18",	"DMIC_DATA1",		"SNDW3_DATA",	"n/a",			"n/a",
+	"GPP_D19",	"DMIC_CLK0",		"SNDW4_CLK",	"n/a",			"n/a",
+	"GPP_D20",	"DMIC_DATA0",		"SNDW4_DATA",	"n/a",			"n/a",
+	"GPP_D21",	"SPI1_IO2",		"n/a",		"n/a",			"n/a",
+	"GPP_D22",	"SPI1_IO3",		"n/a",		"n/a",			"n/a",
+	"GPP_D23",	"ISH_I2C2_SCL",		"I2C3_SCL",	"n/a",			"n/a",
+};
+
+static const struct gpio_group coffeelake_group_d = {
+	.display	= "------- GPIO Group GPP_D -------",
+	.pad_count	= ARRAY_SIZE(coffeelake_group_d_names) / 5,
+	.func_count	= 5,
+	.pad_names	= coffeelake_group_d_names,
+};
+
+static const char *const coffeelake_group_e_names[] = {
+	"GPP_E0",	"SATAXPCIE0",	"SATAGP0",	"n/a",	"n/a",
+	"GPP_E1",	"SATAXPCIE1",	"SATAGP1",	"n/a",	"n/a",
+	"GPP_E2",	"SATAXPCIE2",	"SATAGP2",	"n/a",	"n/a",
+	"GPP_E3",	"CPU_GP0",	"n/a",		"n/a",	"n/a",
+	"GPP_E4",	"SATA_DEVSLP0",	"n/a",		"n/a",	"n/a",
+	"GPP_E5",	"SATA_DEVSLP1",	"n/a",		"n/a",	"n/a",
+	"GPP_E6",	"SATA_DEVSLP2",	"n/a",		"n/a",	"n/a",
+	"GPP_E7",	"CPU_GP1",	"n/a",		"n/a",	"n/a",
+	"GPP_E8",	"SATALED#",	"n/a",		"n/a",	"n/a",
+	"GPP_E9",	"USB2_OC0#",	"n/a",		"n/a",	"n/a",
+	"GPP_E10",	"USB2_OC1#",	"n/a",		"n/a",	"n/a",
+	"GPP_E11",	"USB2_OC2#",	"n/a",		"n/a",	"n/a",
+	"GPP_E12",	"USB2_OC3#",	"n/a",		"n/a",	"n/a",
+};
+
+static const struct gpio_group coffeelake_group_e = {
+	.display	= "-------GPIO Group GPP_E -------",
+	.pad_count	= ARRAY_SIZE(coffeelake_group_e_names) / 5,
+	.func_count	= 5,
+	.pad_names	= coffeelake_group_e_names,
+};
+
+
+static const char *const coffeelake_group_f_names[] = {
+	"GPP_F0",	"SATAXPCIE3",		"SATAGP3",	"n/a",	"n/a",
+	"GPP_F1",	"SATAXPCIE4",		"SATAGP4",	"n/a",	"n/a",
+	"GPP_F2",	"SATAXPCIE5",		"SATAGP5",	"n/a",	"n/a",
+	"GPP_F3",	"SATAXPCIE6",		"SATAGP6",	"n/a",	"n/a",
+	"GPP_F4",	"SATAXPCIE7",		"SATAGP7",	"n/a",	"n/a",
+	"GPP_F5",	"SATA_DEVSLP3",		"n/a",		"n/a",	"n/a",
+	"GPP_F6",	"SATA_DEVSLP4",		"n/a",		"n/a",	"n/a",
+	"GPP_F7",	"SATA_DEVSLP5",		"n/a",		"n/a",	"n/a",
+	"GPP_F8",	"SATA_DEVSLP6",		"n/a",		"n/a",	"n/a",
+	"GPP_F9",	"SATA_DEVSLP7",		"n/a",		"n/a",	"n/a",
+	"GPP_F10",	"SATA_SCLOCK",		"n/a",		"n/a",	"n/a",
+	"GPP_F11",	"SATA_SLOAD",		"n/a",		"n/a",	"n/a",
+	"GPP_F12",	"SATA_SDATAOUT1",	"n/a",		"n/a",	"n/a",
+	"GPP_F13",	"SATA_SDATAOUT0",	"n/a",		"n/a",	"n/a",
+	"GPP_F14",	"n/a",			"PS_ON#",	"n/a",	"n/a",
+	"GPP_F15",	"USB2_OC4#",		"n/a",		"n/a",	"n/a",
+	"GPP_F16",	"USB2_OC5#",		"n/a",		"n/a",	"n/a",
+	"GPP_F17",	"USB2_OC6#",		"n/a",		"n/a",	"n/a",
+	"GPP_F18",	"USB2_OC7#",		"n/a",		"n/a",	"n/a",
+	"GPP_F19",	"eDP_VDDEN",		"n/a",		"n/a",	"n/a",
+	"GPP_F20",	"eDP_BKLTEN",		"n/a",		"n/a",	"n/a",
+	"GPP_F21",	"eDP_BKLTCTL",		"n/a",		"n/a",	"n/a",
+	"GPP_F22",	"DDPF_CTRLCLK",		"n/a",		"n/a",	"n/a",
+	"GPP_F23",	"DDPF_CTRLDATA",	"n/a",		"n/a",	"n/a",
+
+};
+
+static const struct gpio_group coffeelake_group_f = {
+	.display	= "-------GPIO Group GPP_F -------",
+	.pad_count	= ARRAY_SIZE(coffeelake_group_f_names) / 5,
+	.func_count	= 5,
+	.pad_names	= coffeelake_group_f_names,
+};
+
+
+static const char *const coffeelake_group_g_names[] = {
+	"GPP_G0",	"SD_CMD",	"n/a",	"n/a",	"n/a",	
+	"GPP_G1",	"SD_DATA0",	"n/a",	"n/a",	"n/a",	
+	"GPP_G2",	"SD_DATA1",	"n/a",	"n/a",	"n/a",	
+	"GPP_G3",	"SD_DATRA2",	"n/a",	"n/a",	"n/a",	
+	"GPP_G4",	"SD_DATA3",	"n/a",	"n/a",	"n/a",	
+	"GPP_G5",	"SD_CD#",	"n/a",	"n/a",	"n/a",	
+	"GPP_G6",	"SD_CLK",	"n/a",	"n/a",	"n/a",	
+	"GPP_G7",	"SD_WP",	"n/a",	"n/a",	"n/a",	
+};
+
+static const struct gpio_group coffeelake_group_g = {
+	.display	= "-------GPIO Group GPP_G -------",
+	.pad_count	= ARRAY_SIZE(coffeelake_group_g_names) / 5,
+	.func_count	= 5,
+	.pad_names	= coffeelake_group_g_names,
+};
+
+
+static const char *const coffeelake_group_h_names[] = {
+	"GPP_H0",	"SRCCLKREQ6#",	"n/a",	"n/a",	"n/a",
+	"GPP_H1",	"SRCCLKREQ7#",	"n/a",	"n/a",	"n/a",
+	"GPP_H2",	"SRCCLKREQ8#",	"n/a",	"n/a",	"n/a",
+	"GPP_H3",	"SRCCLKREQ9#",	"n/a",	"n/a",	"n/a",
+	"GPP_H4",	"SRCCLKREQ10#",	"n/a",	"n/a",	"n/a",
+	"GPP_H5",	"SRCCLKREQ11#",	"n/a",	"n/a",	"n/a",
+	"GPP_H6",	"SRCCLKREQ12#",	"n/a",	"n/a",	"n/a",
+	"GPP_H7",	"SRCCLKREQ13#",	"n/a",	"n/a",	"n/a",
+	"GPP_H8",	"SRCCLKREQ14#",	"n/a",	"n/a",	"n/a",
+	"GPP_H9",	"SRCCLKREQ15#",	"n/a",	"n/a",	"n/a",
+	"GPP_H10",	"SML2CLK",	"n/a",	"n/a",	"n/a",
+	"GPP_H11",	"SML2DATA",	"n/a",	"n/a",	"n/a",
+	"GPP_H12",	"SML2ALERT#",	"n/a",	"n/a",	"n/a",
+	"GPP_H13",	"SML3CLK",	"n/a",	"n/a",	"n/a",
+	"GPP_H14",	"SML3DATA",	"n/a",	"n/a",	"n/a",
+	"GPP_H15",	"SML3ALERT#",	"n/a",	"n/a",	"n/a",
+	"GPP_H16",	"SML4CLK",	"n/a",	"n/a",	"n/a",
+	"GPP_H17",	"SML4DATA",	"n/a",	"n/a",	"n/a",
+	"GPP_H18",	"SML4ALERT#",	"n/a",	"n/a",	"n/a",
+	"GPP_H19",	"ISH_I2C0_SDA",	"n/a",	"n/a",	"n/a",
+	"GPP_H20",	"ISH_I2C0_SCL",	"n/a",	"n/a",	"n/a",
+	"GPP_H21",	"ISH_I2C1_SDA",	"n/a",	"n/a",	"n/a",
+	"GPP_H22",	"ISH_I2C1_SCL",	"n/a",	"n/a",	"n/a",
+	"GPP_H23",	"TIME_SYNC0",	"n/a",	"n/a",	"n/a",
+};
+
+static const struct gpio_group coffeelake_group_h = {
+	.display	= "-------GPIO Group GPP_H -------",
+	.pad_count	= ARRAY_SIZE(coffeelake_group_h_names) / 5,
+	.func_count	= 5,
+	.pad_names	= coffeelake_group_h_names,
+};
+
+
+static const char *const coffeelake_group_i_names[] = {
+	"GPP_I0",	"DDPB_HPD0",		"DISP_MISC0",	"n/a",	"n/a",
+	"GPP_I1",	"DDPB_HPD1",		"DISP_MISC1",	"n/a",	"n/a",
+	"GPP_I2",	"DDPB_HPD2",		"DISP_MISC2",	"n/a",	"n/a",
+	"GPP_I3",	"DDPB_HPD3",		"DISP_MISC3",	"n/a",	"n/a",
+	"GPP_I4",	"EDP_HPD",		"DISP_MISC4",	"n/a",	"n/a",
+	"GPP_I5",	"DDPB_CTRLCLK",		"n/a",		"n/a",	"n/a",
+	"GPP_I6",	"DDPB_CTRLDATA",	"n/a",		"n/a",	"n/a",
+	"GPP_I7",	"DDPC_CTRLCLK",		"n/a",		"n/a",	"n/a",
+	"GPP_I8",	"DDPC_CTRLDATA",	"n/a",		"n/a",	"n/a",
+	"GPP_I9",	"DDPD_CTRLCLK",		"n/a",		"n/a",	"n/a",
+	"GPP_I10",	"DDPD_CTRLDATA",	"n/a",		"n/a",	"n/a",
+	"GPP_I11",	"M2_SKT2_CFG0",		"n/a",		"n/a",	"n/a",
+	"GPP_I12",	"M2_SKT2_CFG1",		"n/a",		"n/a",	"n/a",
+	"GPP_I13",	"M2_SKT2_CFG2",		"n/a",		"n/a",	"n/a",
+	"GPP_I14",	"M2_SKT2_CFG3",		"n/a",		"n/a",	"n/a",
+};
+
+static const struct gpio_group coffeelake_group_i = {
+	.display	= "-------GPIO Group GPP_I -------",
+	.pad_count	= ARRAY_SIZE(coffeelake_group_i_names) / 5,
+	.func_count	= 5,
+	.pad_names	= coffeelake_group_i_names,
+};
+
+
+static const char *const coffeelake_group_j_names[] = {
+	"GPP_J0",	"CNV_PA_BLANKING",	"n/a",			"n/a",	"n/a",
+	"GPP_J1",	"n/a",			"CPU_C10_GATE#",	"n/a",	"n/a",
+	"GPP_J2",	"n/a",			"n/a",			"n/a",	"n/a",
+	"GPP_J3",	"n/a",			"n/a",			"n/a",	"n/a",
+	"GPP_J4",	"CNV_BRI_DT",		"UART0B_RTS#",		"n/a",	"n/a",
+	"GPP_J5",	"CNV_BRI_RSP",		"UART0B_RXD",		"n/a",	"n/a",
+	"GPP_J6",	"CNV_RGI_DT",		"UART0B_TXD",		"n/a",	"n/a",
+	"GPP_J7",	"CNV_RGI_RSP",		"UART0B_CTS#",		"n/a",	"n/a",
+	"GPP_J8",	"CNV_MFUART2_RXD",	"n/a",			"n/a",	"n/a",
+	"GPP_J9",	"CNV_MFUART2_TXD",	"n/a",			"n/a",	"n/a",
+	"GPP_J10",	"n/a",			"n/a",			"n/a",	"n/a",
+	"GPP_J11",	"A4WP_PRESENT",		"n/a",			"n/a",	"n/a",
+};
+
+static const struct gpio_group coffeelake_group_j = {
+	.display	= "-------GPIO Group GPP_J -------",
+	.pad_count	= ARRAY_SIZE(coffeelake_group_j_names) / 5,
+	.func_count	= 5,
+	.pad_names	= coffeelake_group_j_names,
+};
+
+
+static const char *const coffeelake_group_k_names[] = {
+	"GPP_K0",	"n/a",		"n/a",	"n/a",	"n/a",
+	"GPP_K1",	"n/a",		"n/a",	"n/a",	"n/a",
+	"GPP_K2",	"n/a",		"n/a",	"n/a",	"n/a",
+	"GPP_K3",	"n/a",		"n/a",	"n/a",	"n/a",
+	"GPP_K4",	"n/a",		"n/a",	"n/a",	"n/a",
+	"GPP_K5",	"n/a",		"n/a",	"n/a",	"n/a",
+	"GPP_K6",	"n/a",		"n/a",	"n/a",	"n/a",
+	"GPP_K7",	"n/a",		"n/a",	"n/a",	"n/a",
+	"GPP_K8",	"Reserved",	"n/a",	"n/a",	"n/a",
+	"GPP_K9",	"Reserved",	"n/a",	"n/a",	"n/a",
+	"GPP_K10",	"Reserved",	"n/a",	"n/a",	"n/a",
+	"GPP_K11",	"Reserved",	"n/a",	"n/a",	"n/a",
+	"GPP_K12",	"GSXOUT",	"n/a",	"n/a",	"n/a",
+	"GPP_K13",	"GSXSLOAD",	"n/a",	"n/a",	"n/a",
+	"GPP_K14",	"GSXDIN",	"n/a",	"n/a",	"n/a",
+	"GPP_K15",	"GSXSRESET#",	"n/a",	"n/a",	"n/a",
+	"GPP_K16",	"GSXCLK",	"n/a",	"n/a",	"n/a",
+	"GPP_K17",	"ADR_COMPLETE",	"n/a",	"n/a",	"n/a",
+	"GPP_K18",	"NMI#",		"n/a",	"n/a",	"n/a",
+	"GPP_K19",	"SMI#",		"n/a",	"n/a",	"n/a",
+	"GPP_K20",	"Reserved",	"n/a",	"n/a",	"n/a",
+	"GPP_K21",	"Reserved",	"n/a",	"n/a",	"n/a",
+	"GPP_K22",	"IMGCLKOUT0",	"n/a",	"n/a",	"n/a",
+	"GPP_K23",	"IMGCLKOUT1",	"n/a",	"n/a",	"n/a",
+};
+
+static const struct gpio_group coffeelake_group_k = {
+	.display	= "-------GPIO Group GPP_K -------",
+	.pad_count	= ARRAY_SIZE(coffeelake_group_k_names) / 5,
+	.func_count	= 5,
+	.pad_names	= coffeelake_group_k_names,
+};
+
+static const char *const coffeelake_group_ds_names[] = {
+	"GPD0",		"BATLOW#",	"n/a",	"n/a",	"n/a",
+	"GPD1",		"ACPRESENT",	"n/a",	"n/a",	"n/a",
+	"GPD2",		"LAN_WAKE#",	"n/a",	"n/a",	"n/a",
+	"GPD3",		"PRWBTN#",	"n/a",	"n/a",	"n/a",
+	"GPD4",		"SLP_S3#",	"n/a",	"n/a",	"n/a",
+	"GPD5",		"SLP_S4#",	"n/a",	"n/a",	"n/a",
+	"GPD6",		"SLP_A#",	"n/a",	"n/a",	"n/a",
+	"GPD7",		"n/a",		"n/a",	"n/a",	"n/a",
+	"GPD8",		"SUSCLK",	"n/a",	"n/a",	"n/a",
+	"GPD9",		"SLP_WLAN#",	"n/a",	"n/a",	"n/a",
+	"GPD10",	"SLP_S5#",	"n/a",	"n/a",	"n/a",
+	"GPD11",	"LANPHYPC",	"n/a",	"n/a",	"n/a",
+};
+static const struct gpio_group coffeelake_group_ds = {
+	.display	= "------- GPIO Group GPD -------",
+	.pad_count	= ARRAY_SIZE(coffeelake_group_ds_names) / 5,
+	.func_count	= 5,
+	.pad_names	= coffeelake_group_ds_names,
+};
+
+
+static const struct gpio_group *const coffeelake_community_ab_groups[] = {
+	&coffeelake_group_a,
+	&coffeelake_group_b,
+};
+static	const struct gpio_community coffeelake_community_ab = {
+	.name		= "------- GPIO Community 0 -------",
+	.pcr_port_id	= 0x6e,
+	.group_count	= ARRAY_SIZE(coffeelake_community_ab_groups),
+	.groups		= coffeelake_community_ab_groups,
+};
+
+
+static const struct gpio_group *const coffeelake_community_cdg_groups[] = {
+	&coffeelake_group_c,
+	&coffeelake_group_d,
+	&coffeelake_group_g,
+};
+static	const struct gpio_community coffeelake_community_cdg = {
+	.name		= "------- GPIO Community 1 -------",
+	.pcr_port_id	= 0x6d,
+	.group_count	= ARRAY_SIZE(coffeelake_community_cdg_groups),
+	.groups		= coffeelake_community_cdg_groups,
+};
+
+
+static const struct gpio_group *const coffeelake_community_ds_groups[] = {
+	&coffeelake_group_ds,
+};
+static	const struct gpio_community coffeelake_community_ds = {
+	.name		= "------- GPIO Community 2 -------",
+	.pcr_port_id	= 0x6c,
+	.group_count	= ARRAY_SIZE(coffeelake_community_ds_groups),
+	.groups		= coffeelake_community_ds_groups,
+};
+
+
+static const struct gpio_group *const coffeelake_community_khef_groups[] = {
+	&coffeelake_group_k,
+	&coffeelake_group_h,
+	&coffeelake_group_e,
+	&coffeelake_group_f,
+};
+static	const struct gpio_community coffeelake_community_khef = {
+	.name		= "------- GPIO Community 3 -------",
+	.pcr_port_id	= 0x6b,
+	.group_count	= ARRAY_SIZE(coffeelake_community_khef_groups),
+	.groups		= coffeelake_community_khef_groups,
+};
+
+
+static const struct gpio_group *const coffeelake_community_ij_groups[] = {
+	&coffeelake_group_i,
+	&coffeelake_group_j,
+};
+static	const struct gpio_community coffeelake_community_ij = {
+	.name		= "------- GPIO Community 4 -------",
+	.pcr_port_id	= 0x6a,
+	.group_count	= ARRAY_SIZE(coffeelake_community_ij_groups),
+	.groups		= coffeelake_community_ij_groups,
+};
+
+static const struct gpio_community *const coffeelake_communities[] = {
+	&coffeelake_community_ab,
+	&coffeelake_community_cdg,
+	&coffeelake_community_ds,
+	&coffeelake_community_khef,
+	&coffeelake_community_ij,
+};
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
 static const char *decode_pad_mode(const struct gpio_group *const group,
    			   const size_t pad, const uint32_t dw0)
 {
@@ -860,7 +1310,7 @@
printf("%s\n", group->display);
-	for (p = 0; p < group->pad_count; ++p, pad_cfg += 8) {
+	for (p = 0; p < group->pad_count; ++p, pad_cfg += 16) {
    	const uint32_t dw0 = read_pcr32(pid, pad_cfg);
    	const uint32_t dw1 = read_pcr32(pid, pad_cfg + 4);
@@ -892,7 +1342,7 @@
    for (group = 0; group < community->group_count; ++group) {
    	print_gpio_group(community->pcr_port_id,
    			 pad_cfg, community->groups[group]);
-		pad_cfg += community->groups[group]->pad_count * 8;
+		pad_cfg += community->groups[group]->pad_count * 16;
    }
 }
@@ -923,6 +1373,20 @@
    	communities = denverton_communities;
    	pcr_init(sb);
    	break;
+	case PCI_DEVICE_ID_INTEL_H310:
+	case PCI_DEVICE_ID_INTEL_H370:
+	case PCI_DEVICE_ID_INTEL_Z390:
+	case PCI_DEVICE_ID_INTEL_Q370:
+	case PCI_DEVICE_ID_INTEL_B360:
+	case PCI_DEVICE_ID_INTEL_C246:
+	case PCI_DEVICE_ID_INTEL_C242:
+	case PCI_DEVICE_ID_INTEL_QM370:
+	case PCI_DEVICE_ID_INTEL_HM370:
+	case PCI_DEVICE_ID_INTEL_CM246:
+		community_count = ARRAY_SIZE(coffeelake_communities);
+		communities = coffeelake_communities;
+		pcr_init(sb);
+		break;
    default:
    	return;
    }
diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c
index 5c97a6c..0814c8b 100644
--- a/util/inteltool/pcr.c
+++ b/util/inteltool/pcr.c
@@ -74,7 +74,7 @@
if (sbbar)
    	return;
-
+#if 0
    switch (sb->device_id) {
    case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE:
    case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE:
@@ -103,6 +103,17 @@
    case PCI_DEVICE_ID_INTEL_APL_LPC:
    	p2sb = pci_get_dev(sb->access, 0, 0, 0x0d, 0);
    	break;
+	case PCI_DEVICE_ID_INTEL_H310:
+	case PCI_DEVICE_ID_INTEL_H370:
+	case PCI_DEVICE_ID_INTEL_Z390:
+	case PCI_DEVICE_ID_INTEL_Q370:
+	case PCI_DEVICE_ID_INTEL_B360:
+	case PCI_DEVICE_ID_INTEL_C246:
+	case PCI_DEVICE_ID_INTEL_C242:
+	case PCI_DEVICE_ID_INTEL_QM370:
+	case PCI_DEVICE_ID_INTEL_HM370:
+	case PCI_DEVICE_ID_INTEL_CM246:
+		break;
    default:
    	perror("Unknown LPC device.");
    	exit(1);
@@ -135,23 +146,28 @@
    pci_fill_info(p2sb, PCI_FILL_BASES | PCI_FILL_CLASS);
const pciaddr_t sbbar_phys = p2sb->base_addr[0] & ~0xfULL;
+#endif
+	const pciaddr_t sbbar_phys = 0xfd000000;
+
    printf("SBREG_BAR = 0x%08"PRIx64" (MEM)\n\n", (uint64_t)sbbar_phys);
    sbbar = map_physical(sbbar_phys, SBBAR_SIZE);
    if (sbbar == NULL) {
    	perror("Error mapping SBREG_BAR");
    	error_exit = true;
    }
-
+#if 0
    if (p2sb_revealed) {
    	printf("Hiding Primary to Sideband Bridge (P2SB).\n");
    	pci_write_byte(p2sb, 0xe0 + 1, 1);
    }
    pci_free_dev(p2sb);
-
+#endif
    if (error_exit)
    	exit(1);
 }
+
+
 void pcr_cleanup(void)
 {
    if (sbbar)
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I9f3b3108f5672b557610fa7d8fbd5c199af8d353
Gerrit-Change-Number: 31501
Gerrit-PatchSet: 1
Gerrit-Owner: Thomas Heijligen src@posteo.de
Gerrit-MessageType: newchange



    

Change in ...coreboot[master]: inteltool: coffeelake support