Change in coreboot[master]: soc/mediatek/mt8186: Adjust usage of SRAM L2C

[Hung-Te Lin (Code Review)]

Attention is currently required from: Rex-BC Chen, Paul Menzel.
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60316 )

Change subject: soc/mediatek/mt8186: Adjust usage of SRAM L2C
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Patch Set 5:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/60316/comment/d5e3d4da_d44e8bb6 
PS4, Line 9: However the BootROM
           : has configured only half of L2/L3 cache as SRAM.
> No, it's not a bug. […]

"unchangeable" does not mean it's not a bug - it can still be a silicon bug.
The key is that we still need some space for cache, otherwise the system won't be able to run. One thing can be discussed is if we can configure the cache smaller, for example only 1/4 (256Kb).