[XS] Change in coreboot[main]: soc/intel/xeon_sp: Support GNR PCIe root ports

[Lean Sheng Tan (Code Review)]

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84311?usp=email )

(

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: soc/intel/xeon_sp: Support GNR PCIe root ports
......................................................................

soc/intel/xeon_sp: Support GNR PCIe root ports

Add device IDs for GNR PCIe root ports so that these devices can
be supported by the Xeon-SP PCIe root port driver.

Change-Id: I450c0088aa2e3be60489becf0600f534ea90d7a4
Signed-off-by: Shuo Liu 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84311
Reviewed-by: Lean Sheng Tan 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/xeon_sp/pcie_root_port.c
1 file changed, 8 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Lean Sheng Tan: Looks good to me, approved

diff --git a/src/soc/intel/xeon_sp/pcie_root_port.c b/src/soc/intel/xeon_sp/pcie_root_port.c
index fb9abde..6ecbcec 100644
--- a/src/soc/intel/xeon_sp/pcie_root_port.c
+++ b/src/soc/intel/xeon_sp/pcie_root_port.c
@@ -69,6 +69,14 @@
    0x352c,
    0x352d,
    0x347a,
+	0x0db0,
+	0x0db1,
+	0x0db2,
+	0x0db3,
+	0x0db6,
+	0x0db7,
+	0x0db8,
+	0x0db9,
    0
 };