Change in coreboot[master]: soc/intel/alderlake: Correct TCSS XHCI Port status offset

[Sridhar Siricilla (Code Review)]

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Subrata Banik, Balaji Manigandan, Deepti Deshatty, Patrick Rudolph.
Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55230 )

Change subject: soc/intel/alderlake: Correct TCSS XHCI Port status offset
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Patch Set 2:

(1 comment)

File src/soc/intel/alderlake/xhci.c:

https://review.coreboot.org/c/coreboot/+/55230/comment/2ecb0e02_b577729c 
PS1, Line 18: 0x490
> I don't think this CL is correct. […]

@Subrata, "Port 1 SC"  refers USB2 port status, and USB3 port status starts from 0x490. USB3 port#1: 0x490, USB3 Port#2: 4A0, USB3 Port#3: 0x4B0 USB3 Port#4: 0x4c0