Hello Patrick Rudolph, Aaron Durbin, Nathaniel L Desimone, David Guckian, Subrata Banik, Matt DeVillier, build bot (Jenkins), Hannah Williams, Martin Roth, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29661
to look at the new patch set (#6).
Change subject: soc/intel/braswell: Add support for FSP MR2 ......................................................................
soc/intel/braswell: Add support for FSP MR2
Actual FspUpdVpd.h in Intel vendorcode does not match the MR2 version. Modify vendorcode/intel/makefile.inc using CONFIG_FSP_VENDORCODE_HEADER_PATH to specify the path to UPD include file. soc/intel/braswell/chip.c has been modified using the common MR1 and MR2 fields only. The 'non MR2' fields must be configured in mainboard.
BUG=NA TEST=Portwell PQ7-M107
Change-Id: Id40b5d46ddda93845d9739b56aaf7ad24ee89246 Signed-off-by: Frans Hendriks fhendriks@eltan.com --- M src/mainboard/google/cyan/Makefile.inc A src/mainboard/google/cyan/ramstage.c M src/mainboard/intel/strago/ramstage.c M src/soc/intel/braswell/chip.c M src/vendorcode/intel/Makefile.inc 5 files changed, 78 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/29661/6